[llvm] 816985c - [NFC][llvm][MIRVRegNamerUtils] Refactoring GetHashableMO into switch-statement.

[Puyan Lotfi via llvm-commits]

Author: Puyan Lotfi
Date: 2019-12-14T02:31:07-05:00
New Revision: 816985c12053e0f0654e28e1a517799954ea5360

URL: https://github.com/llvm/llvm-project/commit/816985c12053e0f0654e28e1a517799954ea5360
DIFF: https://github.com/llvm/llvm-project/commit/816985c12053e0f0654e28e1a517799954ea5360.diff

LOG: [NFC][llvm][MIRVRegNamerUtils] Refactoring GetHashableMO into switch-statement.

This refactors the if-statements handling the hashing of various
MachineOperand types into a switch-statement. The purpose is to cover
all the basis for all MachineOperand types while being very deliberate
about which MachineOperand types we are not handling and why (better
added comments). This patch is a NFC redo of https://reviews.llvm.org/D71396.
Much of the changes present in D71396 will come in smaller follow-up patches
that will add support for hashing the MachineOperand types that aren't
covered piece-meal with tests for each new case.

Added: 
    

Modified: 
    llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
index 8b17f78e0bcf..fa36a110664b 100644
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -52,21 +52,48 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
 
   // Gets a hashable artifact from a given MachineOperand (ie an unsigned).
   auto GetHashableMO = [this](const MachineOperand &MO) -> unsigned {
-    if (MO.isImm())
+    switch (MO.getType()) {
+    case MachineOperand::MO_Immediate:
       return MO.getImm();
-    if (MO.isTargetIndex())
+    case MachineOperand::MO_TargetIndex:
       return MO.getOffset() | (MO.getTargetFlags() << 16);
-    if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
-      return MRI.getVRegDef(MO.getReg())->getOpcode();
-    if (MO.isReg())
+    case MachineOperand::MO_Register:
+      if (Register::isVirtualRegister(MO.getReg()))
+        return MRI.getVRegDef(MO.getReg())->getOpcode();
       return MO.getReg();
-    // TODO:
+
     // We could explicitly handle all the types of the MachineOperand,
     // here but we can just return a common number until we find a
     // compelling test case where this is bad. The only side effect here
     // is contributing to a hash collision but there's enough information
     // (Opcodes,other registers etc) that this will likely not be a problem.
-    return 0;
+
+    // TODO: Handle the following Immediate/Index/ID/Predicate cases. They can
+    // be hashed on in a stable manner.
+    case MachineOperand::MO_CImmediate:
+    case MachineOperand::MO_FPImmediate:
+    case MachineOperand::MO_FrameIndex:
+    case MachineOperand::MO_ConstantPoolIndex:
+    case MachineOperand::MO_JumpTableIndex:
+    case MachineOperand::MO_CFIIndex:
+    case MachineOperand::MO_IntrinsicID:
+    case MachineOperand::MO_Predicate:
+
+    // In the cases below we havn't found a way to produce an artifact that will
+    // result in a stable hash, in most cases because they are pointers. We want
+    // stable hashes because we want the hash to be the same run to run.
+    case MachineOperand::MO_MachineBasicBlock:
+    case MachineOperand::MO_ExternalSymbol:
+    case MachineOperand::MO_GlobalAddress:
+    case MachineOperand::MO_BlockAddress:
+    case MachineOperand::MO_RegisterMask:
+    case MachineOperand::MO_RegisterLiveOut:
+    case MachineOperand::MO_Metadata:
+    case MachineOperand::MO_MCSymbol:
+    case MachineOperand::MO_ShuffleMask:
+      return 0;
+    }
+    llvm_unreachable("Unexpected MachineOperandType.");
   };
 
   SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};