[PATCH] D71509: [ELF][PowerPC] Set PltSection alignment to 4 and fix IPLT index

[Fangrui Song via Phabricator via llvm-commits]

MaskRay created this revision.
Herald added subscribers: llvm-commits, steven.zhang, shchenz, jsji, arphaman, kristof.beyls, arichardson, nemanjai, emaste.
Herald added a reviewer: espindola.
Herald added a project: LLVM.

On targets that support IFUNC, ARM and AArch64 don't use PLT index.
i386 and x86-64 use PLT index but PLT index is ignored for IFUNC because
IFUNC don't use lazily resolved JUMP_SLOT.

Only PowerPC is affected.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71509

Files:
  lld/ELF/SyntheticSections.cpp
  lld/ELF/SyntheticSections.h


Index: lld/ELF/SyntheticSections.h
===================================================================
--- lld/ELF/SyntheticSections.h
+++ lld/ELF/SyntheticSections.h
@@ -671,6 +671,7 @@
   PltSection(bool isIplt);
   void writeTo(uint8_t *buf) override;
   size_t getSize() const override;
+  uint32_t getNumEntries() const { return entries.size(); }
   bool isNeeded() const override { return !entries.empty(); }
   void addSymbols();
   template <class ELFT> void addEntry(Symbol &sym);
Index: lld/ELF/SyntheticSections.cpp
===================================================================
--- lld/ELF/SyntheticSections.cpp
+++ lld/ELF/SyntheticSections.cpp
@@ -2446,13 +2446,14 @@
 // On PowerPC64 the lazy symbol resolvers go into the `global linkage table`
 // in the .glink section, rather then the typical .plt section.
 PltSection::PltSection(bool isIplt)
-    : SyntheticSection(
-          SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16,
-          (config->emachine == EM_PPC || config->emachine == EM_PPC64)
-              ? ".glink"
-              : ".plt"),
+    : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16, ".plt"),
       headerSize(!isIplt || config->zRetpolineplt ? target->pltHeaderSize : 0),
       isIplt(isIplt) {
+  if (config->emachine == EM_PPC || config->emachine == EM_PPC64) {
+    name = ".glink";
+    alignment = 4;
+  }
+
   // The PLT needs to be writable on SPARC as the dynamic linker will
   // modify the instructions in the PLT entries.
   if (config->emachine == EM_SPARCV9)
@@ -2481,7 +2482,8 @@
     unsigned relOff = relSec->entsize * i + pltOff;
     uint64_t got = b->getGotPltVA();
     uint64_t plt = this->getVA() + off;
-    target->writePlt(buf + off, got, plt, b->pltIndex, relOff);
+    uint32_t index = (isIplt ? in.plt->getNumEntries() : 0) + b->pltIndex;
+    target->writePlt(buf + off, got, plt, index, relOff);
     off += target->pltEntrySize;
   }
 }


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