[llvm] 84593f0 - [ARM][MVE] Make VPT invalid for tail predication

[Sam Parker via llvm-commits]

Author: Sam Parker
Date: 2019-12-13T15:01:08Z
New Revision: 84593f058b97d6470156e68841cfacee48af39a7

URL: https://github.com/llvm/llvm-project/commit/84593f058b97d6470156e68841cfacee48af39a7
DIFF: https://github.com/llvm/llvm-project/commit/84593f058b97d6470156e68841cfacee48af39a7.diff

LOG: [ARM][MVE] Make VPT invalid for tail predication

We've been marking VPT incompatible instructions as invalid for tail
predication too, though this may not strictly be true. VPT are
incompatible and, unless its the first predicate def in a loop,
they shouldn't be compatible for tail predication either.

Differential Revision: https://reviews.llvm.org/D71410

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/unittests/Target/ARM/MachineInstrTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index a40231c4aa13..82a622d799a5 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -5394,7 +5394,6 @@ class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> patte
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1<string suffix, bits<2> size, dag iops>
@@ -5406,7 +5405,6 @@ class MVE_VPTt1<string suffix, bits<2> size, dag iops>
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = fc{1};
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1i<string suffix, bits<2> size>
@@ -5508,7 +5506,6 @@ class MVE_VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=
 
   let Defs = [VPR];
   let Predicates = [HasMVEFloat];
-  let validForTailPredication = 1;
 }
 
 class MVE_VPTft1<string suffix, bit size>

diff  --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index fc7dc9e67ca5..8807a2f31826 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -272,28 +272,6 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VPNOT:
     case MVE_VPSEL:
     case MVE_VPST:	
-    case MVE_VPTv16i8:
-    case MVE_VPTv16i8r:
-    case MVE_VPTv16s8:
-    case MVE_VPTv16s8r:
-    case MVE_VPTv16u8:	
-    case MVE_VPTv16u8r:
-    case MVE_VPTv4f32:
-    case MVE_VPTv4f32r:
-    case MVE_VPTv4i32:
-    case MVE_VPTv4i32r:
-    case MVE_VPTv4s32:
-    case MVE_VPTv4s32r:
-    case MVE_VPTv4u32:
-    case MVE_VPTv4u32r:
-    case MVE_VPTv8f16:
-    case MVE_VPTv8f16r:
-    case MVE_VPTv8i16:
-    case MVE_VPTv8i16r:
-    case MVE_VPTv8s16:
-    case MVE_VPTv8s16r:
-    case MVE_VPTv8u16:
-    case MVE_VPTv8u16r:
     case MVE_VQABSs16:
     case MVE_VQABSs32:
     case MVE_VQABSs8: