[llvm] 9432937 - Revert "[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc"

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2019-12-12T16:24:40-05:00
New Revision: 9432937190d8c891a93521bed7b9b76397e410e3

URL: https://github.com/llvm/llvm-project/commit/9432937190d8c891a93521bed7b9b76397e410e3
DIFF: https://github.com/llvm/llvm-project/commit/9432937190d8c891a93521bed7b9b76397e410e3.diff

LOG: Revert "[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc"

This reverts commit 8963332c3327daa652ba3e26d35f9109b6991985.
There was a logic bug typo in this code, but it wasn't visible in the asm for the tests.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AArch64/shift-amount-mod.ll
    llvm/test/CodeGen/PowerPC/trunc-srl-load.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index fdc9f48fbcc6..c462a6bcb9f0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7943,18 +7943,6 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
                                        InnerShift.getOperand(0), NewShiftAmt);
         return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift);
       }
-      // In the more general case, we can clear the high bits after the shift:
-      // srl (trunc (srl x, c1)), c2 --> trunc (and (srl x, (c1+c2)), Mask)
-      if (N0.hasOneUse() && InnerShift.hasOneUse() && c1 + c2 <= OpSizeInBits) {
-        SDLoc DL(N);
-        SDValue NewShiftAmt = DAG.getConstant(c1 + c2, DL, ShiftAmtVT);
-        SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
-                                       InnerShift.getOperand(0), NewShiftAmt);
-        SDValue Mask = DAG.getConstant((1 << (InnerShiftSize - c2)) - 1, DL,
-                                       InnerShiftVT);
-        SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask);
-        return DAG.getNode(ISD::TRUNCATE, DL, VT, And);
-      }
     }
   }
 

diff  --git a/llvm/test/CodeGen/AArch64/shift-amount-mod.ll b/llvm/test/CodeGen/AArch64/shift-amount-mod.ll
index 403839044cdf..4f6051e2a6cf 100644
--- a/llvm/test/CodeGen/AArch64/shift-amount-mod.ll
+++ b/llvm/test/CodeGen/AArch64/shift-amount-mod.ll
@@ -670,7 +670,8 @@ define i64 @reg64_lshr_by_masked_negated_unfolded_add_b(i64 %val, i64 %a, i64 %b
 define i32 @t(i64 %x) {
 ; CHECK-LABEL: t:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ubfx x0, x0, #17, #28
+; CHECK-NEXT:    lsr x8, x0, #13
+; CHECK-NEXT:    ubfx x0, x8, #4, #28
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
 ; CHECK-NEXT:    ret
   %s = lshr i64 %x, 13

diff  --git a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
index 5dc0534ef446..a1af256eccb2 100644
--- a/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
+++ b/llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
@@ -25,7 +25,8 @@ cond.false:                                       ; preds = %entry
 define i32 @sh_trunc_sh(i64 %x) {
 ; CHECK-LABEL: sh_trunc_sh:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 47, 36
+; CHECK-NEXT:    rldicl 3, 3, 51, 13
+; CHECK-NEXT:    srwi 3, 3, 4
 ; CHECK-NEXT:    blr
   %s = lshr i64 %x, 13
   %t = trunc i64 %s to i32