[PATCH] D71432: [AArch64][SVE] Proposal to use op+select to match scalable predicated operations

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: sdesmalen, c-rhodes, rovka, rengolin, eli.friedman, Andrzej, kmclaughlin, steleman.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

As promised from the SVE LLVM Sync-up today, here is a proposal to support scalable op+select masks in the backend. A solution like this would allow us to generate predicated instructions directly from IR, without the need for target intrinsics.

Also note that this is a temporary solution. The native vector predication project `D57504` will eventually obsolete this work.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71432

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fp-pred.ll

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