[PATCH] D71401: [AArch64][SVE] Add permutation and selection intrinsics
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 12 09:56:03 PST 2019
efriedma added inline comments.
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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:782
LLVMMatchType<0>,
llvm_i32_ty],
[IntrNoMem]>;
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I guess this is sort of orthogonal to your patch, but this is missing ImmArg marking
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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1182
def int_aarch64_sve_sunpklo : AdvSIMD_SVE_Unpack_Intrinsic;
-
+def int_aarch64_sve_tbl : AdvSIMD_SVE_TBL_Intrinsic;
+def int_aarch64_sve_trn1 : AdvSIMD_2VectorArg_Intrinsic;
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Any thoughts on naming tbl for one-register and two-register forms?
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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:12470
+ ConstantSDNode *CN = cast<ConstantSDNode>(N->getOperand(0));
+ Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
+ switch (IntID) {
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Can you check here that the result type is i8 or i16?
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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:5040
+ def : SVE_3_Op_Pat<nxv4f32, op, nxv4i1, nxv4f32, nxv4f32, !cast<Instruction>(NAME # _S)>;
+ def : SVE_3_Op_Pat<nxv2f64, op, nxv2i1, nxv2f64, nxv2f64, !cast<Instruction>(NAME # _D)>;
}
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This unconditionally maps the "splice" intrinsic to the destructive form? I guess that's fine.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D71401/new/
https://reviews.llvm.org/D71401
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