[llvm] bbd16b6 - [AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 12 01:49:58 PST 2019
Author: Cullen Rhodes
Date: 2019-12-12T09:49:22Z
New Revision: bbd16b687641377c0ba54c8ceb1fc1ec4c0eb19a
URL: https://github.com/llvm/llvm-project/commit/bbd16b687641377c0ba54c8ceb1fc1ec4c0eb19a
DIFF: https://github.com/llvm/llvm-project/commit/bbd16b687641377c0ba54c8ceb1fc1ec4c0eb19a.diff
LOG: [AArch64][SVE] Remove nxv1f32 and nxv1f64 as legal types
Summary: Also cleans up ZPR register class definition.
Reviewers: sdesmalen, cameron.mcinally, efriedma
Reviewed By: efriedma
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71351
Added:
Modified:
llvm/lib/Target/AArch64/AArch64CallingConvention.td
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
index 3c179ae76f0e..a0b2d7712b66 100644
--- a/llvm/lib/Target/AArch64/AArch64CallingConvention.td
+++ b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -75,10 +75,10 @@ def CC_AArch64_AAPCS : CallingConv<[
CCIfConsecutiveRegs<CCCustom<"CC_AArch64_Custom_Block">>,
CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64],
+ nxv2f32, nxv4f32, nxv2f64],
CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64],
+ nxv2f32, nxv4f32, nxv2f64],
CCPassIndirect<i64>>,
CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],
@@ -155,7 +155,7 @@ def RetCC_AArch64_AAPCS : CallingConv<[
CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
CCIfType<[nxv16i8, nxv8i16, nxv4i32, nxv2i64, nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32, nxv1f64, nxv2f64],
+ nxv2f32, nxv4f32, nxv2f64],
CCAssignToReg<[Z0, Z1, Z2, Z3, Z4, Z5, Z6, Z7]>>,
CCIfType<[nxv2i1, nxv4i1, nxv8i1, nxv16i1],
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index de2bc1610c82..5e55a6702010 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -179,10 +179,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::nxv2f16, &AArch64::ZPRRegClass);
addRegisterClass(MVT::nxv4f16, &AArch64::ZPRRegClass);
addRegisterClass(MVT::nxv8f16, &AArch64::ZPRRegClass);
- addRegisterClass(MVT::nxv1f32, &AArch64::ZPRRegClass);
addRegisterClass(MVT::nxv2f32, &AArch64::ZPRRegClass);
addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass);
- addRegisterClass(MVT::nxv1f64, &AArch64::ZPRRegClass);
addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass);
for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64 }) {
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 61fc0795c242..b92ae1dbc5c6 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -858,35 +858,19 @@ def PPR3b64 : PPRRegOp<"d", PPRAsmOp3b64, ElementSizeD, PPR_3b>;
//******************************************************************************
-// SVE vector register class
-def ZPR : RegisterClass<"AArch64",
- [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
- nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32,
- nxv1f64, nxv2f64],
- 128, (sequence "Z%u", 0, 31)> {
+// SVE vector register classes
+class ZPRClass<int lastreg> : RegisterClass<"AArch64",
+ [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
+ nxv2f16, nxv4f16, nxv8f16,
+ nxv2f32, nxv4f32,
+ nxv2f64],
+ 128, (sequence "Z%u", 0, lastreg)> {
let Size = 128;
}
-// SVE restricted 4 bit scalable vector register class
-def ZPR_4b : RegisterClass<"AArch64",
- [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
- nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32,
- nxv1f64, nxv2f64],
- 128, (sequence "Z%u", 0, 15)> {
- let Size = 128;
-}
-
-// SVE restricted 3 bit scalable vector register class
-def ZPR_3b : RegisterClass<"AArch64",
- [nxv16i8, nxv8i16, nxv4i32, nxv2i64,
- nxv2f16, nxv4f16, nxv8f16,
- nxv1f32, nxv2f32, nxv4f32,
- nxv1f64, nxv2f64],
- 128, (sequence "Z%u", 0, 7)> {
- let Size = 128;
-}
+def ZPR : ZPRClass<31>;
+def ZPR_4b : ZPRClass<15>; // Restricted 4 bit SVE vector register class.
+def ZPR_3b : ZPRClass<7>; // Restricted 3 bit SVE vector register class.
class ZPRAsmOperand<string name, int Width, string RegClassSuffix = "">
: AsmOperandClass {
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