[PATCH] D71391: [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0

[Jim Lin via Phabricator via llvm-commits]

Jim requested changes to this revision.
Jim added a comment.
This revision now requires changes to proceed.

It looks like not only this 6 instructions have to set hasSideEffects to 0.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1369
 // Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
+let hasSideEffects = 0 in {
 def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
----------------
hasSideEffects = 0 should be added class `VX1_RT5_RA5_VB5`.
Something like:
```
let hasSideEffects = 0 in
class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
...
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71391/new/

https://reviews.llvm.org/D71391