[PATCH] D71391: [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
ZhangKang added reviewers: PowerPC, hfinkel.
Herald added subscribers: shchenz, wuzish.
Herald added a project: LLVM.
ZhangKang updated this revision to Diff 233501.
ZhangKang added a comment.

Modify the patch.


If we didn't set the value for hasSideEffects bit in our td file,  `llvm-tblgen` will set it as true for those instructions which has no match pattern. 
Below 6 instructions don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by llvm-tblgen.

But in fact below instructions don't modify any special register and don't have other SideEffects, they shouldn't have SideEffects.
This patch is to modify the hasSideEffects of below instructions from 1 to 0.

  VEXTUHLX
  VEXTUHRX
  VEXTUWLX
  VEXTUWRX
  VSPLTBs
  VSPLTHs


https://reviews.llvm.org/D71391

Files:
  llvm/lib/Target/PowerPC/PPCInstrAltivec.td
  llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

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