[PATCH] D71390: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang created this revision.
Herald added subscribers: llvm-commits, shchenz, jsji, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.
ZhangKang added reviewers: PowerPC, hfinkel.
ZhangKang added subscribers: power-llvm-team, echristo.
Herald added a subscriber: wuzish.

If we didn't set the value for hasSideEffects bit in our td file,  `llvm-tblgen` will set it as true for those instructions which has no match pattern. 
The instructions `MTLR` and `MFLR` do't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. 
But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects.

This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.


https://reviews.llvm.org/D71390

Files:
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/CSR-fit.ll
  llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll
  llvm/test/CodeGen/PowerPC/csr-split.ll
  llvm/test/CodeGen/PowerPC/machine-pre.ll
  llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll
  llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/PowerPC/pr43527.ll
  llvm/test/CodeGen/PowerPC/pr44183.ll
  llvm/test/CodeGen/PowerPC/sjlj.ll
  llvm/test/CodeGen/PowerPC/sms-phi-1.ll
  llvm/test/CodeGen/PowerPC/sms-phi-3.ll
  llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D71390.233497.patch
Type: text/x-patch
Size: 23591 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191212/1fc04647/attachment-0001.bin>