[PATCH] D71266: [ARM] Return a number of micro-ops for vlldm/vlstm
Momchil Velikov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 11 03:51:35 PST 2019
chill added a comment.
In D71266#1778483 <https://reviews.llvm.org/D71266#1778483>, @efriedma wrote:
> Is there some reason we can't handle these using tablegen'ed data, like other instructions?
In a sense we do use tablegen, it just that tablegen says "defer that to C++ code". (cf. "dynamic uops" in `ARMScheduleA8.td` and `ARMScheduleA9.td`).
In D71266#1779054 <https://reviews.llvm.org/D71266#1779054>, @dmgreen wrote:
> It looks like in the instruction definitions, the VLSTM and VLLDM have IIC_fpLoad_m and IIC_fpStore_m.
Yeah, I was thinking of setting these to `NoItinerary`. I thought I wouldn't like to disturb existing scheduling, but on a second thought,
indeed, we'd better have new-style scheduling models for armv8-m cores.
I will see about removing `IIC_fpLoad`, etc.
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https://reviews.llvm.org/D71266/new/
https://reviews.llvm.org/D71266
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