[PATCH] D59780: Support Intel Control-flow Enforcement Technology
Fangrui Song via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 21:19:43 PST 2019
MaskRay added a comment.
In D59780#1778882 <https://reviews.llvm.org/D59780#1778882>, @tstellar wrote:
> In D59780#1778863 <https://reviews.llvm.org/D59780#1778863>, @ruiu wrote:
>
> > Hmm, I'm sorry but I'm confused. IIRC I had a discussion in the LLVM dev meeting that we were going to submit a change with a single PLT scheme rather than IPLT, so when I said that I'm going to submit a patch, I meant that I'm going to submit a patch for the 1PLT scheme rather than the 2PLT scheme. But this is for the 2PLT scheme. This is not something I want.
>
>
> What was the decision that was made at the developer meeting? Will lld support the 2PLT scheme defined in the psABI?
(Personally, I am still unhappy with the .plt.sec scheme. I think I prefer a 1PLT scheme like AArch64's Branch Target Indicators (BTI) and Pointer Authentication Code (PAC).) But I thought @ruiu accepted the fait accompli because there had been very strong objection to diverge from what GNU ld does. https://groups.google.com/forum/#!topic/x86-64-abi/sQcX3__r4c0
`objdump -d` (built from binutils-gdb HEAD) still does not work with lld produced binaries.
% objdump -d a.bfd # -z ibt
Disassembly of section .plt:
0000000000001020 <.plt>:
1020: ff 35 e2 2f 00 00 pushq 0x2fe2(%rip) # 4008 <_GLOBAL_OFFSET_TABLE_+0x8>
1026: f2 ff 25 e3 2f 00 00 bnd jmpq *0x2fe3(%rip) # 4010 <_GLOBAL_OFFSET_TABLE_+0x10>
102d: 0f 1f 00 nopl (%rax)
1030: f3 0f 1e fa endbr64
1034: 68 00 00 00 00 pushq $0x0
1039: f2 e9 e1 ff ff ff bnd jmpq 1020 <.plt>
103f: 90 nop
1040: f3 0f 1e fa endbr64
1044: 68 01 00 00 00 pushq $0x1
1049: f2 e9 d1 ff ff ff bnd jmpq 1020 <.plt>
104f: 90 nop
Disassembly of section .plt.got:
0000000000001050 <__cxa_finalize at plt>:
1050: f3 0f 1e fa endbr64
1054: f2 ff 25 9d 2f 00 00 bnd jmpq *0x2f9d(%rip) # 3ff8 <__cxa_finalize at GLIBC_2.2.5>
105b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1)
Disassembly of section .plt.sec:
0000000000001060 <puts at plt>:
1060: f3 0f 1e fa endbr64
1064: f2 ff 25 ad 2f 00 00 bnd jmpq *0x2fad(%rip) # 4018 <puts at GLIBC_2.2.5>
106b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1)
0000000000001070 <exit at plt>:
1070: f3 0f 1e fa endbr64
1074: f2 ff 25 a5 2f 00 00 bnd jmpq *0x2fa5(%rip) # 4020 <exit at GLIBC_2.2.5>
107b: 0f 1f 44 00 00 nopl 0x0(%rax,%rax,1)
% objdump -d a.lld # --require-cet (actually my patched version, which behaves like AArch64's --force-bti
...
Disassembly of section .plt:
00000000000018c0 <.plt>:
18c0: ff 35 0a 22 00 00 pushq 0x220a(%rip) # 3ad0 <__init_array_end+0x1190>
18c6: ff 25 0c 22 00 00 jmpq *0x220c(%rip) # 3ad8 <__init_array_end+0x1198>
18cc: 0f 1f 40 00 nopl 0x0(%rax)
18d0: f3 0f 1e fa endbr64
18d4: 68 00 00 00 00 pushq $0x0
18d9: e9 e2 ff ff ff jmpq 18c0 <_fini+0x14>
18de: 66 90 xchg %ax,%ax
18e0: f3 0f 1e fa endbr64
18e4: 68 01 00 00 00 pushq $0x1
18e9: e9 d2 ff ff ff jmpq 18c0 <_fini+0x14>
18ee: 66 90 xchg %ax,%ax
18f0: f3 0f 1e fa endbr64
18f4: 68 02 00 00 00 pushq $0x2
18f9: e9 c2 ff ff ff jmpq 18c0 <_fini+0x14>
18fe: 66 90 xchg %ax,%ax
Disassembly of section .plt.sec:
0000000000001900 <.plt.sec>:
1900: f3 0f 1e fa endbr64
1904: ff 25 16 22 00 00 jmpq *0x2216(%rip) # 3b20 <__cxa_finalize at GLIBC_2.2.5>
190a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1)
1910: f3 0f 1e fa endbr64
1914: ff 25 0e 22 00 00 jmpq *0x220e(%rip) # 3b28 <puts at GLIBC_2.2.5>
191a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1)
1920: f3 0f 1e fa endbr64
1924: ff 25 06 22 00 00 jmpq *0x2206(%rip) # 3b30 <exit at GLIBC_2.2.5>
192a: 66 0f 1f 44 00 00 nopw 0x0(%rax,%rax,1)
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https://reviews.llvm.org/D59780/new/
https://reviews.llvm.org/D59780
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