[PATCH] D71320: [IR] Split out target specific intrinsic enums into separate headers

Reid Kleckner via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 10 16:55:33 PST 2019


rnk created this revision.
rnk added reviewers: efriedma, echristo.
Herald added subscribers: cfe-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, dmgreen, Petar.Avramovic, jsji, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, kbarton, aheejin, hiraditya, jgravelle-google, sbc100, aprantl, mgorny, nhaehnle, jvesely, nemanjai, sdardis, dschuff, arsenm, jholewinski.
Herald added projects: clang, LLVM.

This has two main effects:

- Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size.
- Incremental step towards decoupling target intrinsics.

The enums are still compact, so adding and removing a single
target-specific intrinsic will trigger a rebuild of all of LLVM.
Assigning distinct target id spaces is potential future work.

Part of PR34259

Depends on D71318 <https://reviews.llvm.org/D71318>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D71320

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGException.cpp
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp
  llvm/include/llvm/Analysis/TargetTransformInfo.h
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/Analysis/VectorUtils.h
  llvm/include/llvm/IR/CMakeLists.txt
  llvm/include/llvm/IR/CallSite.h
  llvm/include/llvm/IR/Function.h
  llvm/include/llvm/IR/GlobalValue.h
  llvm/include/llvm/IR/InstrTypes.h
  llvm/include/llvm/IR/Intrinsics.h
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/Analysis/MemoryLocation.cpp
  llvm/lib/Analysis/TargetTransformInfo.cpp
  llvm/lib/Analysis/ValueTracking.cpp
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/TypePromotion.cpp
  llvm/lib/CodeGen/WasmEHPrepare.cpp
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/IR/Function.cpp
  llvm/lib/IR/Verifier.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/AArch64StackTagging.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/lib/Target/AMDGPU/AMDGPU.h
  llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
  llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp
  llvm/lib/Target/ARM/ARMParallelDSP.cpp
  llvm/lib/Target/ARM/MVETailPredication.cpp
  llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
  llvm/lib/Target/Hexagon/HexagonGenExtract.cpp
  llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
  llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp
  llvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp
  llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp
  llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp
  llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
  llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  llvm/lib/Target/Mips/MipsSEISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
  llvm/lib/Target/NVPTX/NVPTXImageOptimizer.cpp
  llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp
  llvm/lib/Target/NVPTX/NVVMIntrRange.cpp
  llvm/lib/Target/NVPTX/NVVMReflect.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZTDC.cpp
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
  llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/lib/Target/X86/X86FastISel.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86InstructionSelector.cpp
  llvm/lib/Target/X86/X86IntrinsicsInfo.h
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/lib/Target/X86/X86WinEHState.cpp
  llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
  llvm/lib/Target/XCore/XCoreISelLowering.cpp
  llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
  llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
  llvm/unittests/IR/IRBuilderTest.cpp
  llvm/utils/TableGen/IntrinsicEmitter.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D71320.233231.patch
Type: text/x-patch
Size: 55705 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191211/ada0b3b7/attachment-0001.bin>


More information about the llvm-commits mailing list