[llvm] f364686 - [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.

[Puyan Lotfi via llvm-commits]

Author: Puyan Lotfi
Date: 2019-12-10T20:16:14-05:00
New Revision: f364686f34d80e0873b478933952c6b664177ce4

URL: https://github.com/llvm/llvm-project/commit/f364686f34d80e0873b478933952c6b664177ce4
DIFF: https://github.com/llvm/llvm-project/commit/f364686f34d80e0873b478933952c6b664177ce4.diff

LOG: [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.

Now, flags will result in differing hashes for a given MI. In effect, if
you have two instructions with everything identical except for their
flags then you should get two different hashes and fewer collisions.

Differential Revision: https://reviews.llvm.org/D70479

Added: 
    llvm/test/CodeGen/MIR/X86/mircanon-flags.mir

Modified: 
    llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
index 998d391bf834..be29f8cd64b5 100644
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -69,7 +69,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
     return 0;
   };
 
-  SmallVector<unsigned, 16> MIOperands = {MI.getOpcode()};
+  SmallVector<unsigned, 16> MIOperands = {MI.getOpcode(), MI.getFlags()};
   llvm::transform(MI.uses(), std::back_inserter(MIOperands), GetHashableMO);
 
   auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end());

diff  --git a/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
new file mode 100644
index 000000000000..d3c797ba8df5
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/mircanon-flags.mir
@@ -0,0 +1,37 @@
+# RUN: llc -march=x86-64 -run-pass mir-canonicalizer -o - %s | FileCheck %s
+# The purpose of this test is to ensure that 
diff ering flags do in-fact cause
+# naming collisions with the new vreg renamers naming scheme.
+--- |
+  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+  define void @baz() { unreachable }
+...
+---
+name:            baz
+body:             |
+  bb.0:
+
+    ; CHECK: COPY
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
+    ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
+
+    %0:fr32 = COPY $xmm0
+    %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr
+    %2:fr32 = ninf VMULSSrr %1, %1, implicit $mxcsr
+    %3:fr32 = nsz VMULSSrr %2, %2, implicit $mxcsr
+    %4:fr32 = arcp VMULSSrr %3, %3, implicit $mxcsr
+    %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
+    %6:fr32 = afn VMULSSrr %5, %5, implicit $mxcsr
+    %7:fr32 = reassoc VMULSSrr %6, %6, implicit $mxcsr
+    %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
+    %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
+    $xmm0 = COPY %9
+    RET 0, $xmm0
+
+...