[llvm] 21bc863 - [FPEnv][X86] Constrained FCmp intrinsics enabling on X86
via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 10 16:23:29 PST 2019
Author: Wang, Pengfei
Date: 2019-12-11T08:23:09+08:00
New Revision: 21bc8631fe934126a19ddc9cfd08b20798c5043d
URL: https://github.com/llvm/llvm-project/commit/21bc8631fe934126a19ddc9cfd08b20798c5043d
DIFF: https://github.com/llvm/llvm-project/commit/21bc8631fe934126a19ddc9cfd08b20798c5043d.diff
LOG: [FPEnv][X86] Constrained FCmp intrinsics enabling on X86
Summary: This is a follow up of D69281, it enables the X86 backend support for the FP comparision.
Reviewers: uweigand, kpn, craig.topper, RKSimon, cameron.mcinally, andrew.w.kaylor
Subscribers: hiraditya, llvm-commits, annita.zhang, LuoYuanke, LiuChen3
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70582
Added:
llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
llvm/test/CodeGen/X86/vec-strict-128-cmp.ll
llvm/test/CodeGen/X86/vec-strict-256-cmp.ll
llvm/test/CodeGen/X86/vec-strict-512-cmp.ll
Modified:
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/Target/X86/X86FloatingPoint.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.h
llvm/lib/Target/X86/X86InstrAVX512.td
llvm/lib/Target/X86/X86InstrFPStack.td
llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86InstrSSE.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 3c5675395e11..260a8108873c 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -983,13 +983,17 @@ class SelectionDAG {
/// Helper function to make it easier to build SetCC's if you just have an
/// ISD::CondCode instead of an SDValue.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
- ISD::CondCode Cond) {
+ ISD::CondCode Cond, SDValue Chain = SDValue(),
+ bool IsSignaling = false) {
assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&
"Cannot compare scalars to vectors");
assert(LHS.getValueType().isVector() == VT.isVector() &&
"Cannot compare scalars to vectors");
assert(Cond != ISD::SETCC_INVALID &&
"Cannot create a setCC of an invalid node.");
+ if (Chain)
+ return getNode(IsSignaling ? ISD::STRICT_FSETCCS : ISD::STRICT_FSETCC, DL,
+ {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b3860dda8e0f..70966b68c930 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -134,7 +134,8 @@ class SelectionDAGLegalize {
ArrayRef<int> Mask) const;
bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
- bool &NeedInvert, const SDLoc &dl);
+ bool &NeedInvert, const SDLoc &dl, SDValue &Chain,
+ bool IsSignaling = false);
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
@@ -1638,10 +1639,9 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
/// of a true/false result.
///
/// \returns true if the SetCC has been legalized, false if it hasn't.
-bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
- SDValue &RHS, SDValue &CC,
- bool &NeedInvert,
- const SDLoc &dl) {
+bool SelectionDAGLegalize::LegalizeSetCCCondCode(
+ EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, bool &NeedInvert,
+ const SDLoc &dl, SDValue &Chain, bool IsSignaling) {
MVT OpVT = LHS.getSimpleValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
NeedInvert = false;
@@ -1724,13 +1724,16 @@ bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
// If we aren't the ordered or unorder operation,
// then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
- SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
- SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
+ SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1, Chain, IsSignaling);
+ SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2, Chain, IsSignaling);
} else {
// Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
- SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
- SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
+ SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1, Chain, IsSignaling);
+ SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2, Chain, IsSignaling);
}
+ if (Chain)
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, SetCC1.getValue(1),
+ SetCC2.getValue(1));
LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
RHS = SDValue();
CC = SDValue();
@@ -3524,12 +3527,19 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
}
Results.push_back(Tmp1);
break;
- case ISD::SETCC: {
- Tmp1 = Node->getOperand(0);
- Tmp2 = Node->getOperand(1);
- Tmp3 = Node->getOperand(2);
- bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
- Tmp3, NeedInvert, dl);
+ case ISD::SETCC:
+ case ISD::STRICT_FSETCC:
+ case ISD::STRICT_FSETCCS: {
+ bool IsStrict = Node->getOpcode() != ISD::SETCC;
+ bool IsSignaling = Node->getOpcode() == ISD::STRICT_FSETCCS;
+ SDValue Chain = IsStrict ? Node->getOperand(0) : SDValue();
+ unsigned Offset = IsStrict ? 1 : 0;
+ Tmp1 = Node->getOperand(0 + Offset);
+ Tmp2 = Node->getOperand(1 + Offset);
+ Tmp3 = Node->getOperand(2 + Offset);
+ bool Legalized =
+ LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3,
+ NeedInvert, dl, Chain, IsSignaling);
if (Legalized) {
// If we expanded the SETCC by swapping LHS and RHS, or by inverting the
@@ -3544,9 +3554,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
Results.push_back(Tmp1);
+ if (IsStrict)
+ Results.push_back(Chain);
+
break;
}
+ // FIXME: It seems Legalized is false iff CCCode is Legal. I don't
+ // understand if this code is useful for strict nodes.
+ assert(!IsStrict && "Don't know how to expand for strict nodes.");
+
// Otherwise, SETCC for the given comparison type must be completely
// illegal; expand it into a SELECT_CC.
EVT VT = Node->getValueType(0);
@@ -3569,11 +3586,13 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
break;
}
case ISD::SELECT_CC: {
+ // TODO: need to add STRICT_SELECT_CC and STRICT_SELECT_CCS
Tmp1 = Node->getOperand(0); // LHS
Tmp2 = Node->getOperand(1); // RHS
Tmp3 = Node->getOperand(2); // True
Tmp4 = Node->getOperand(3); // False
EVT VT = Node->getValueType(0);
+ SDValue Chain;
SDValue CC = Node->getOperand(4);
ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
@@ -3616,9 +3635,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
}
if (!Legalized) {
- Legalized = LegalizeSetCCCondCode(
- getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
- dl);
+ Legalized = LegalizeSetCCCondCode(getSetCCResultType(Tmp1.getValueType()),
+ Tmp1, Tmp2, CC, NeedInvert, dl, Chain);
assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
@@ -3644,13 +3662,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
break;
}
case ISD::BR_CC: {
+ // TODO: need to add STRICT_BR_CC and STRICT_BR_CCS
+ SDValue Chain;
Tmp1 = Node->getOperand(0); // Chain
Tmp2 = Node->getOperand(2); // LHS
Tmp3 = Node->getOperand(3); // RHS
Tmp4 = Node->getOperand(1); // CC
- bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
- Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
+ bool Legalized =
+ LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()), Tmp2,
+ Tmp3, Tmp4, NeedInvert, dl, Chain);
(void)Legalized;
assert(Legalized && "Can't legalize BR_CC with legal condition!");
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index 3b73ab00b926..1e18a6769c94 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -667,6 +667,12 @@ static const TableEntry OpcodeTable[] = {
{ X86::CMOVP_Fp32 , X86::CMOVP_F },
{ X86::CMOVP_Fp64 , X86::CMOVP_F },
{ X86::CMOVP_Fp80 , X86::CMOVP_F },
+ { X86::COM_FpIr32 , X86::COM_FIr },
+ { X86::COM_FpIr64 , X86::COM_FIr },
+ { X86::COM_FpIr80 , X86::COM_FIr },
+ { X86::COM_Fpr32 , X86::COM_FST0r },
+ { X86::COM_Fpr64 , X86::COM_FST0r },
+ { X86::COM_Fpr80 , X86::COM_FST0r },
{ X86::DIVR_Fp32m , X86::DIVR_F32m },
{ X86::DIVR_Fp64m , X86::DIVR_F64m },
{ X86::DIVR_Fp64m32 , X86::DIVR_F32m },
@@ -798,6 +804,10 @@ static unsigned getConcreteOpcode(unsigned Opcode) {
static const TableEntry PopTable[] = {
{ X86::ADD_FrST0 , X86::ADD_FPrST0 },
+ { X86::COMP_FST0r, X86::FCOMPP },
+ { X86::COM_FIr , X86::COM_FIPr },
+ { X86::COM_FST0r , X86::COMP_FST0r },
+
{ X86::DIVR_FrST0, X86::DIVR_FPrST0 },
{ X86::DIV_FrST0 , X86::DIV_FPrST0 },
@@ -836,7 +846,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
int Opcode = Lookup(PopTable, I->getOpcode());
if (Opcode != -1) {
I->setDesc(TII->get(Opcode));
- if (Opcode == X86::UCOM_FPPr)
+ if (Opcode == X86::FCOMPP || Opcode == X86::UCOM_FPPr)
I->RemoveOperand(0);
} else { // Insert an explicit pop
I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 0c7aaada4be9..fb68ea5c2854 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -542,6 +542,10 @@ static bool isLegalMaskCompare(SDNode *N, const X86Subtarget *Subtarget) {
// this happens we will use 512-bit operations and the mask will not be
// zero extended.
EVT OpVT = N->getOperand(0).getValueType();
+ // The first operand of X86ISD::CMPM is chain, so we need to get the second
+ // operand.
+ if (Opcode == X86ISD::CMPM)
+ OpVT = N->getOperand(1).getValueType();
if (OpVT.is256BitVector() || OpVT.is128BitVector())
return Subtarget->hasVLX();
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 703a3af19184..f434b7de51b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -410,6 +410,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
for (auto VT : { MVT::f32, MVT::f64, MVT::f80, MVT::f128 }) {
setOperationAction(ISD::SELECT, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
}
for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
if (VT == MVT::i64 && !Subtarget.is64Bit())
@@ -929,6 +931,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
setOperationAction(ISD::SETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::ABS, VT, Custom);
@@ -1212,6 +1216,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
setOperationAction(ISD::SETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
setOperationAction(ISD::CTPOP, VT, Custom);
setOperationAction(ISD::CTLZ, VT, Custom);
@@ -1374,6 +1380,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SUB, VT, Custom);
setOperationAction(ISD::MUL, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
setOperationAction(ISD::SELECT, VT, Custom);
setOperationAction(ISD::TRUNCATE, VT, Custom);
setOperationAction(ISD::UADDSAT, VT, Custom);
@@ -1513,6 +1521,8 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::ROTL, VT, Custom);
setOperationAction(ISD::ROTR, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, VT, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, VT, Custom);
setOperationAction(ISD::SELECT, VT, Custom);
// The condition codes aren't legal in SSE/AVX and under AVX512 we use
@@ -20264,14 +20274,20 @@ static SDValue EmitTest(SDValue Op, unsigned X86CC, const SDLoc &dl,
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent.
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
- const SDLoc &dl, SelectionDAG &DAG) const {
+ const SDLoc &dl, SelectionDAG &DAG,
+ SDValue Chain, bool IsSignaling) const {
if (isNullConstant(Op1))
return EmitTest(Op0, X86CC, dl, DAG, Subtarget);
EVT CmpVT = Op0.getValueType();
- if (CmpVT.isFloatingPoint())
+ if (CmpVT.isFloatingPoint()) {
+ if (Chain)
+ return DAG.getNode(IsSignaling ? X86ISD::STRICT_FCMPS
+ : X86ISD::STRICT_FCMP,
+ dl, {MVT::i32, MVT::Other}, {Chain, Op0, Op1});
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
+ }
assert((CmpVT == MVT::i8 || CmpVT == MVT::i16 ||
CmpVT == MVT::i32 || CmpVT == MVT::i64) && "Unexpected VT!");
@@ -20333,16 +20349,19 @@ SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
SelectionDAG &DAG) const {
// If the subtarget does not support the FUCOMI instruction, floating-point
// comparisons have to be converted.
- if (Subtarget.hasCMov() ||
- Cmp.getOpcode() != X86ISD::CMP ||
- !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
- !Cmp.getOperand(1).getValueType().isFloatingPoint())
+ bool IsCmp = Cmp.getOpcode() == X86ISD::CMP;
+ bool IsStrictCmp = Cmp.getOpcode() == X86ISD::STRICT_FCMP ||
+ Cmp.getOpcode() == X86ISD::STRICT_FCMPS;
+
+ if (Subtarget.hasCMov() || (!IsCmp && !IsStrictCmp) ||
+ !Cmp.getOperand(IsStrictCmp ? 1 : 0).getValueType().isFloatingPoint() ||
+ !Cmp.getOperand(IsStrictCmp ? 2 : 1).getValueType().isFloatingPoint())
return Cmp;
// The instruction selector will select an FUCOM instruction instead of
// FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
// build an SDNode sequence that transfers the result from FPSW into EFLAGS:
- // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
+ // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86any_fcmp ...)), 8))))
SDLoc dl(Cmp);
SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
@@ -20586,7 +20605,7 @@ static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
/// Turns an ISD::CondCode into a value suitable for SSE floating-point mask
/// CMPs.
static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
- SDValue &Op1) {
+ SDValue &Op1, bool &IsAlwaysSignaling) {
unsigned SSECC;
bool Swap = false;
@@ -20625,6 +20644,22 @@ static unsigned translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
if (Swap)
std::swap(Op0, Op1);
+ switch (SetCCOpcode) {
+ default:
+ IsAlwaysSignaling = true;
+ break;
+ case ISD::SETEQ:
+ case ISD::SETOEQ:
+ case ISD::SETUEQ:
+ case ISD::SETNE:
+ case ISD::SETONE:
+ case ISD::SETUNE:
+ case ISD::SETO:
+ case ISD::SETUO:
+ IsAlwaysSignaling = false;
+ break;
+ }
+
return SSECC;
}
@@ -20769,12 +20804,16 @@ static SDValue LowerVSETCCWithSUBUS(SDValue Op0, SDValue Op1, MVT VT,
static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
- SDValue Op0 = Op.getOperand(0);
- SDValue Op1 = Op.getOperand(1);
- SDValue CC = Op.getOperand(2);
- MVT VT = Op.getSimpleValueType();
+ bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC ||
+ Op.getOpcode() == ISD::STRICT_FSETCCS;
+ bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS;
+ SDValue Chain = IsStrict ? Op.getOperand(0) : DAG.getEntryNode();
+ SDValue Op0 = Op.getOperand(IsStrict ? 1 : 0);
+ SDValue Op1 = Op.getOperand(IsStrict ? 2 : 1);
+ SDValue CC = Op.getOperand(IsStrict ? 3 : 2);
+ MVT VT = Op->getSimpleValueType(0);
ISD::CondCode Cond = cast<CondCodeSDNode>(CC)->get();
- bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
+ bool isFP = Op1.getSimpleValueType().isFloatingPoint();
SDLoc dl(Op);
if (isFP) {
@@ -20795,34 +20834,74 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
VT = Op0.getSimpleValueType();
}
- // In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
- // emit two comparisons and a logic op to tie them together.
SDValue Cmp;
- unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1);
- if (SSECC >= 8 && !Subtarget.hasAVX()) {
- // LLVM predicate is SETUEQ or SETONE.
- unsigned CC0, CC1;
- unsigned CombineOpc;
- if (Cond == ISD::SETUEQ) {
- CC0 = 3; // UNORD
- CC1 = 0; // EQ
- CombineOpc = X86ISD::FOR;
+ bool IsAlwaysSignaling;
+ unsigned SSECC = translateX86FSETCC(Cond, Op0, Op1, IsAlwaysSignaling);
+ if (!Subtarget.hasAVX()) {
+ // TODO: We could use following steps to handle a quiet compare with
+ // signaling encodings.
+ // 1. Get ordered masks from a quiet ISD::SETO
+ // 2. Use the masks to mask potential unordered elements in operand A, B
+ // 3. Get the compare results of masked A, B
+ // 4. Calculating final result using the mask and result from 3
+ // But currently, we just fall back to scalar operations.
+ if (IsStrict && IsAlwaysSignaling && !IsSignaling)
+ return SDValue();
+
+ // Insert an extra signaling instruction to raise exception.
+ if (IsStrict && !IsAlwaysSignaling && IsSignaling) {
+ SDValue SignalCmp = DAG.getNode(
+ Opc, dl, {VT, MVT::Other},
+ {Chain, Op0, Op1, DAG.getTargetConstant(1, dl, MVT::i8)}); // LT_OS
+ // FIXME: It seems we need to update the flags of all new strict nodes.
+ // Otherwise, mayRaiseFPException in MI will return false due to
+ // NoFPExcept = false by default. However, I didn't find it in other
+ // patches.
+ SignalCmp->setFlags(Op->getFlags());
+ Chain = SignalCmp.getValue(1);
+ }
+
+ // In the two cases not handled by SSE compare predicates (SETUEQ/SETONE),
+ // emit two comparisons and a logic op to tie them together.
+ if (SSECC >= 8) {
+ // LLVM predicate is SETUEQ or SETONE.
+ unsigned CC0, CC1;
+ unsigned CombineOpc;
+ if (Cond == ISD::SETUEQ) {
+ CC0 = 3; // UNORD
+ CC1 = 0; // EQ
+ CombineOpc = X86ISD::FOR;
+ } else {
+ assert(Cond == ISD::SETONE);
+ CC0 = 7; // ORD
+ CC1 = 4; // NEQ
+ CombineOpc = X86ISD::FAND;
+ }
+
+ SDValue Cmp0 = DAG.getNode(
+ Opc, dl, {VT, MVT::Other},
+ {Chain, Op0, Op1, DAG.getTargetConstant(CC0, dl, MVT::i8)});
+ SDValue Cmp1 = DAG.getNode(
+ Opc, dl, {VT, MVT::Other},
+ {Chain, Op0, Op1, DAG.getTargetConstant(CC1, dl, MVT::i8)});
+ Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Cmp0.getValue(1),
+ Cmp1.getValue(1));
+ Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
} else {
- assert(Cond == ISD::SETONE);
- CC0 = 7; // ORD
- CC1 = 4; // NEQ
- CombineOpc = X86ISD::FAND;
+ Cmp = DAG.getNode(
+ Opc, dl, {VT, MVT::Other},
+ {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});
+ Chain = Cmp.getValue(1);
}
-
- SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
- DAG.getTargetConstant(CC0, dl, MVT::i8));
- SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
- DAG.getTargetConstant(CC1, dl, MVT::i8));
- Cmp = DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
} else {
// Handle all other FP comparisons here.
- Cmp = DAG.getNode(Opc, dl, VT, Op0, Op1,
- DAG.getTargetConstant(SSECC, dl, MVT::i8));
+ if (IsStrict)
+ // Make a flip on already signaling CCs before setting bit 4 of AVX CC.
+ SSECC |= (IsAlwaysSignaling ^ IsSignaling) << 4;
+ Cmp = DAG.getNode(
+ Opc, dl, {VT, MVT::Other},
+ {Chain, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)});
+ Chain = Cmp.getValue(1);
}
// If this is SSE/AVX CMPP, bitcast the result back to integer to match the
@@ -20831,9 +20910,14 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget,
if (Opc == X86ISD::CMPP)
Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp);
+ if (IsStrict)
+ return DAG.getMergeValues({Cmp, Chain}, dl);
+
return Cmp;
}
+ assert(!IsStrict && "Strict SETCC only handles FP operands.");
+
MVT VTOp0 = Op0.getSimpleValueType();
(void)VTOp0;
assert(VTOp0 == Op1.getSimpleValueType() &&
@@ -21143,8 +21227,9 @@ static SDValue EmitAVX512Test(SDValue Op0, SDValue Op1, ISD::CondCode CC,
/// corresponding X86 condition code constant in X86CC.
SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
ISD::CondCode CC, const SDLoc &dl,
- SelectionDAG &DAG,
- SDValue &X86CC) const {
+ SelectionDAG &DAG, SDValue &X86CC,
+ SDValue &Chain,
+ bool IsSignaling) const {
// Optimize to BT if possible.
// Lower (X & (1 << N)) == 0 to BT(X, N).
// Lower ((X >>u N) & 1) != 0 to BT(X, N).
@@ -21192,7 +21277,9 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
if (CondCode == X86::COND_INVALID)
return SDValue();
- SDValue EFLAGS = EmitCmp(Op0, Op1, CondCode, dl, DAG);
+ SDValue EFLAGS = EmitCmp(Op0, Op1, CondCode, dl, DAG, Chain, IsSignaling);
+ if (Chain)
+ Chain = EFLAGS.getValue(1);
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
X86CC = DAG.getTargetConstant(CondCode, dl, MVT::i8);
return EFLAGS;
@@ -21200,19 +21287,26 @@ SDValue X86TargetLowering::emitFlagsForSetcc(SDValue Op0, SDValue Op1,
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
- MVT VT = Op.getSimpleValueType();
+ bool IsStrict = Op.getOpcode() == ISD::STRICT_FSETCC ||
+ Op.getOpcode() == ISD::STRICT_FSETCCS;
+ MVT VT = Op->getSimpleValueType(0);
if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
- SDValue Op0 = Op.getOperand(0);
- SDValue Op1 = Op.getOperand(1);
+ SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
+ SDValue Op0 = Op.getOperand(IsStrict ? 1 : 0);
+ SDValue Op1 = Op.getOperand(IsStrict ? 2 : 1);
SDLoc dl(Op);
- ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+ ISD::CondCode CC =
+ cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
// Handle f128 first, since one possible outcome is a normal integer
// comparison which gets handled by emitFlagsForSetcc.
if (Op0.getValueType() == MVT::f128) {
+ // FIXME: We may need a strict version of softenSetCCOperands before
+ // supporting f128.
+ assert(!IsStrict && "Unhandled strict operation!");
softenSetCCOperands(DAG, MVT::f128, Op0, Op1, CC, dl, Op0, Op1);
// If softenSetCCOperands returned a scalar, use it.
@@ -21224,11 +21318,17 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
}
SDValue X86CC;
- SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC);
+ SDValue EFLAGS = emitFlagsForSetcc(Op0, Op1, CC, dl, DAG, X86CC, Chain,
+ Op.getOpcode() == ISD::STRICT_FSETCCS);
if (!EFLAGS)
return SDValue();
- return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS);
+ SDValue Res = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, X86CC, EFLAGS);
+
+ if (IsStrict)
+ return DAG.getMergeValues({Res, Chain}, dl);
+
+ return Res;
}
SDValue X86TargetLowering::LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const {
@@ -21359,8 +21459,10 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
(Subtarget.hasSSE1() && VT == MVT::f32)) &&
VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
- unsigned SSECC = translateX86FSETCC(
- cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
+ bool IsAlwaysSignaling;
+ unsigned SSECC =
+ translateX86FSETCC(cast<CondCodeSDNode>(Cond.getOperand(2))->get(),
+ CondOp0, CondOp1, IsAlwaysSignaling);
if (Subtarget.hasAVX512()) {
SDValue Cmp =
@@ -21449,7 +21551,9 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
}
}
- if (Cond.getOpcode() == ISD::SETCC) {
+ if (Cond.getOpcode() == ISD::SETCC ||
+ Cond.getOpcode() == ISD::STRICT_FSETCC ||
+ Cond.getOpcode() == ISD::STRICT_FSETCCS) {
if (SDValue NewCond = LowerSETCC(Cond, DAG)) {
Cond = NewCond;
// If the condition was updated, it's possible that the operands of the
@@ -22924,6 +23028,24 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
unsigned IntNo = Op.getConstantOperandVal(0);
MVT VT = Op.getSimpleValueType();
const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
+
+ // We share some nodes between STRICT and non STRICT FP intrinsics.
+ // For these nodes, we need chain them to entry token if they are not called
+ // by STRICT FP intrinsics.
+ auto getProperNode = [&](unsigned Opcode, EVT VT, ArrayRef<SDValue> Ops) {
+ switch (Opcode) {
+ default:
+ return DAG.getNode(Opcode, dl, VT, Ops);
+ case X86ISD::CMPP:
+ case X86ISD::CMPM:
+ break;
+ }
+
+ SmallVector<SDValue, 6> NewOps = {DAG.getEntryNode()};
+ NewOps.append(Ops.begin(), Ops.end());
+ return DAG.getNode(Opcode, dl, {VT, MVT::Other}, NewOps);
+ };
+
if (IntrData) {
switch(IntrData->Type) {
case INTR_TYPE_1OP: {
@@ -23012,8 +23134,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return SDValue();
}
- return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),
- Src1, Src2, Src3);
+ return getProperNode(IntrData->Opc0, Op.getValueType(),
+ {Src1, Src2, Src3});
}
case INTR_TYPE_4OP:
return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
@@ -23261,8 +23383,8 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return SDValue();
}
//default rounding mode
- return DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
- Op.getOperand(2), CC);
+ return getProperNode(IntrData->Opc0, MaskVT,
+ {Op.getOperand(1), Op.getOperand(2), CC});
}
case CMP_MASK_SCALAR_CC: {
SDValue Src1 = Op.getOperand(1);
@@ -27902,7 +28024,9 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
- case ISD::SETCC: return LowerSETCC(Op, DAG);
+ case ISD::SETCC:
+ case ISD::STRICT_FSETCC:
+ case ISD::STRICT_FSETCCS: return LowerSETCC(Op, DAG);
case ISD::SETCCCARRY: return LowerSETCCCARRY(Op, DAG);
case ISD::SELECT: return LowerSELECT(Op, DAG);
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
@@ -28804,6 +28928,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
case X86ISD::CALL: return "X86ISD::CALL";
case X86ISD::BT: return "X86ISD::BT";
case X86ISD::CMP: return "X86ISD::CMP";
+ case X86ISD::STRICT_FCMP: return "X86ISD::STRICT_FCMP";
+ case X86ISD::STRICT_FCMPS: return "X86ISD::STRICT_FCMPS";
case X86ISD::COMI: return "X86ISD::COMI";
case X86ISD::UCOMI: return "X86ISD::UCOMI";
case X86ISD::CMPM: return "X86ISD::CMPM";
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 2bf4977449d0..016120064134 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -79,6 +79,9 @@ namespace llvm {
/// X86 compare and logical compare instructions.
CMP, COMI, UCOMI,
+ /// X86 strict FP compare instructions.
+ STRICT_FCMP, STRICT_FCMPS,
+
/// X86 bit-test instructions.
BT,
@@ -1340,6 +1343,7 @@ namespace llvm {
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSTRICT_FSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
@@ -1480,17 +1484,18 @@ namespace llvm {
/// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent, for use with the given x86 condition code.
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, const SDLoc &dl,
- SelectionDAG &DAG) const;
+ SelectionDAG &DAG, SDValue Chain = SDValue(),
+ bool IsSignaling = false) const;
/// Convert a comparison if required by the subtarget.
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
/// Emit flags for the given setcc condition and operands. Also returns the
/// corresponding X86 condition code constant in X86CC.
- SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1,
- ISD::CondCode CC, const SDLoc &dl,
- SelectionDAG &DAG,
- SDValue &X86CC) const;
+ SDValue emitFlagsForSetcc(SDValue Op0, SDValue Op1, ISD::CondCode CC,
+ const SDLoc &dl, SelectionDAG &DAG,
+ SDValue &X86CC, SDValue &Chain,
+ bool IsSignaling) const;
/// Check if replacement of SQRT with RSQRT should be disabled.
bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override;
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index ab94950a635e..13dad572f29f 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -8719,20 +8719,18 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
}
let Defs = [EFLAGS], Predicates = [HasAVX512] in {
- defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
+ defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86any_fcmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>;
- defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
+ defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86any_fcmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
- let Pattern = []<dag> in {
- defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
- "comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
- EVEX_CD8<32, CD8VT1>;
- defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
- "comisd", SSEPackedDouble>, PD, EVEX,
- VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
- }
+ defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, X86strict_fcmps, f32, f32mem, loadf32,
+ "comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
+ EVEX_CD8<32, CD8VT1>;
+ defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, X86strict_fcmps, f64, f64mem, loadf64,
+ "comisd", SSEPackedDouble>, PD, EVEX,
+ VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
let isCodeGenOnly = 1 in {
defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
sse_load_f32, "ucomiss", SSEPackedSingle>, PS, EVEX, VEX_LIG,
diff --git a/llvm/lib/Target/X86/X86InstrFPStack.td b/llvm/lib/Target/X86/X86InstrFPStack.td
index d9cf56083130..1bd9ea47c2e7 100644
--- a/llvm/lib/Target/X86/X86InstrFPStack.td
+++ b/llvm/lib/Target/X86/X86InstrFPStack.td
@@ -637,11 +637,17 @@ def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
// Floating point compares.
let SchedRW = [WriteFCom], Uses = [FPCW] in {
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
- [(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
+ [(set FPSW, (trunc (X86any_fcmp RFP32:$lhs, RFP32:$rhs)))]>;
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
- [(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>;
+ [(set FPSW, (trunc (X86any_fcmp RFP64:$lhs, RFP64:$rhs)))]>;
def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
+ [(set FPSW, (trunc (X86any_fcmp RFP80:$lhs, RFP80:$rhs)))]>;
+def COM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
+ [(set FPSW, (trunc (X86strict_fcmps RFP32:$lhs, RFP32:$rhs)))]>;
+def COM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
+ [(set FPSW, (trunc (X86strict_fcmps RFP64:$lhs, RFP64:$rhs)))]>;
+def COM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
+ [(set FPSW, (trunc (X86strict_fcmps RFP80:$lhs, RFP80:$rhs)))]>;
} // SchedRW
} // mayRaiseFPException = 1
@@ -649,13 +655,22 @@ let SchedRW = [WriteFCom], mayRaiseFPException = 1 in {
// CC = ST(0) cmp ST(i)
let Defs = [EFLAGS, FPCW], Uses = [FPCW] in {
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
- [(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
+ [(set EFLAGS, (X86any_fcmp RFP32:$lhs, RFP32:$rhs))]>,
Requires<[FPStackf32, HasCMov]>;
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
- [(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>,
+ [(set EFLAGS, (X86any_fcmp RFP64:$lhs, RFP64:$rhs))]>,
Requires<[FPStackf64, HasCMov]>;
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
- [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>,
+ [(set EFLAGS, (X86any_fcmp RFP80:$lhs, RFP80:$rhs))]>,
+ Requires<[HasCMov]>;
+def COM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
+ [(set EFLAGS, (X86strict_fcmps RFP32:$lhs, RFP32:$rhs))]>,
+ Requires<[FPStackf32, HasCMov]>;
+def COM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
+ [(set EFLAGS, (X86strict_fcmps RFP64:$lhs, RFP64:$rhs))]>,
+ Requires<[FPStackf64, HasCMov]>;
+def COM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
+ [(set EFLAGS, (X86strict_fcmps RFP80:$lhs, RFP80:$rhs))]>,
Requires<[HasCMov]>;
}
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 1a4f7e1e6bbd..96af2129f2d2 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -169,7 +169,7 @@ def X86vshiftimm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
def X86vshldq : SDNode<"X86ISD::VSHLDQ", X86vshiftimm>;
def X86vshrdq : SDNode<"X86ISD::VSRLDQ", X86vshiftimm>;
-def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
+def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP, [SDNPHasChain]>;
def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
@@ -181,7 +181,7 @@ def X86CmpMaskCCScalar :
SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisFP<1>, SDTCisSameAs<1, 2>,
SDTCisVT<3, i8>]>;
-def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
+def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC, [SDNPHasChain]>;
def X86cmpmSAE : SDNode<"X86ISD::CMPM_SAE", X86CmpMaskCC>;
def X86cmpms : SDNode<"X86ISD::FSETCCM", X86CmpMaskCCScalar>;
def X86cmpmsSAE : SDNode<"X86ISD::FSETCCM_SAE", X86CmpMaskCCScalar>;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 3ab45ba833fb..347f29e56a72 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -142,6 +142,8 @@ def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
+def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86CmpTest, [SDNPHasChain]>;
+def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86CmpTest, [SDNPHasChain]>;
def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
@@ -375,6 +377,9 @@ class X86VMemOperand<RegisterClass RC, string printMethod,
}
def anymem : X86MemOperand<"printanymem">;
+def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs),
+ [(X86cmp node:$lhs, node:$rhs),
+ (X86strict_fcmp node:$lhs, node:$rhs)]>;
// FIXME: Right now we allow any size during parsing, but we might want to
// restrict to only unsized memory.
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index f97d90076c18..83c6f27cbe8c 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -1874,16 +1874,14 @@ let mayLoad = 1 in
}
let Defs = [EFLAGS] in {
- defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
+ defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86any_fcmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
- defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
+ defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86any_fcmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
- let Pattern = []<dag> in {
- defm VCOMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
- "comiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
- defm VCOMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
- "comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
- }
+ defm VCOMISS : sse12_ord_cmp<0x2F, FR32, X86strict_fcmps, f32, f32mem, loadf32,
+ "comiss", SSEPackedSingle>, PS, VEX, VEX_LIG, VEX_WIG;
+ defm VCOMISD : sse12_ord_cmp<0x2F, FR64, X86strict_fcmps, f64, f64mem, loadf64,
+ "comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
let isCodeGenOnly = 1 in {
defm VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
@@ -1896,17 +1894,14 @@ let Defs = [EFLAGS] in {
defm VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
sse_load_f64, "comisd", SSEPackedDouble>, PD, VEX, VEX_LIG, VEX_WIG;
}
- defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
+ defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86any_fcmp, f32, f32mem, loadf32,
"ucomiss", SSEPackedSingle>, PS;
- defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
+ defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86any_fcmp, f64, f64mem, loadf64,
"ucomisd", SSEPackedDouble>, PD;
-
- let Pattern = []<dag> in {
- defm COMISS : sse12_ord_cmp<0x2F, FR32, undef, f32, f32mem, loadf32,
- "comiss", SSEPackedSingle>, PS;
- defm COMISD : sse12_ord_cmp<0x2F, FR64, undef, f64, f64mem, loadf64,
- "comisd", SSEPackedDouble>, PD;
- }
+ defm COMISS : sse12_ord_cmp<0x2F, FR32, X86strict_fcmps, f32, f32mem, loadf32,
+ "comiss", SSEPackedSingle>, PS;
+ defm COMISD : sse12_ord_cmp<0x2F, FR64, X86strict_fcmps, f64, f64mem, loadf64,
+ "comisd", SSEPackedDouble>, PD;
let isCodeGenOnly = 1 in {
defm UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
new file mode 100644
index 000000000000..df214c57d53a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
@@ -0,0 +1,3063 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=X87
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse,+cmov -O3 | FileCheck %s --check-prefixes=X87-CMOV
+
+define i32 @test_f32_oeq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oeq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oeq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oeq_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB0_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB0_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB0_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oeq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ogt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ogt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ogt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ogt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB1_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB1_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ogt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oge_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB2_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB2_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_olt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_olt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_olt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_olt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB3_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB3_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_olt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ole_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ole_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ole_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ole_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB4_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB4_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ole_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_one_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_one_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_one_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_one_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB5_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB5_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_one_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ord_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ord_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ord_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ord_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB6_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB6_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ord_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ueq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ueq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ueq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ueq_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB7_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB7_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ueq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ugt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ugt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ugt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ugt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB8_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB8_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ugt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uge_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB9_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB9_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ult_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ult_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ult_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ult_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB10_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB10_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ult_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ule_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ule_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ule_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ule_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB11_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB11_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ule_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_une_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_une_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_une_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_une_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB12_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB12_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB12_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_une_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uno_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uno_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uno_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uno_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB13_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB13_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uno_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oeq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oeq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oeq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oeq_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB14_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB14_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB14_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oeq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ogt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ogt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ogt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ogt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB15_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB15_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ogt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oge_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB16_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB16_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_olt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_olt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_olt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_olt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB17_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB17_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_olt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ole_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ole_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ole_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ole_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB18_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB18_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ole_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_one_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_one_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_one_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_one_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB19_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB19_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_one_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ord_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ord_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ord_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ord_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB20_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB20_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ord_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ueq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ueq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ueq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ueq_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB21_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB21_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ueq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ugt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ugt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ugt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ugt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB22_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB22_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ugt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uge_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB23_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB23_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ult_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ult_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ult_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ult_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB24_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB24_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ult_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ule_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ule_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ule_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ule_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB25_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB25_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ule_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_une_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_une_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_une_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_une_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB26_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB26_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB26_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_une_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uno_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uno_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uno_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uno_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB27_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB27_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uno_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oeq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oeq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oeq_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB28_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB28_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB28_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oeq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ogt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ogt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ogt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB29_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB29_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ogt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oge_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB30_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB30_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_olt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_olt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_olt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB31_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB31_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_olt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ole_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ole_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ole_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB32_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB32_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ole_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_one_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_one_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_one_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB33_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB33_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_one_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ord_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ord_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ord_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB34_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB34_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ord_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ueq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ueq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ueq_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB35_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB35_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ueq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ugt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ugt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ugt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB36_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB36_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ugt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uge_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB37_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB37_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ult_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ult_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ult_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB38_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB38_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ult_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ule_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ule_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ule_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB39_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB39_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ule_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_une_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_une_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_une_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB40_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB40_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB40_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_une_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uno_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uno_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uno_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB41_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB41_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uno_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oeq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oeq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oeq_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB42_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB42_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB42_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oeq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ogt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ogt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ogt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB43_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB43_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ogt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oge_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB44_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB44_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_olt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_olt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_olt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB45_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB45_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_olt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ole_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ole_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ole_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB46_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB46_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ole_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_one_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_one_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_one_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB47_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB47_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_one_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ord_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ord_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ord_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB48_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB48_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ord_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ueq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ueq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ueq_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB49_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB49_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ueq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ugt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ugt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ugt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB50_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB50_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ugt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uge_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB51_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB51_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ult_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ult_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ult_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB52_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB52_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ult_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ule_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ule_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ule_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB53_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB53_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ule_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_une_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_une_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_une_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB54_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB54_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB54_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_une_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uno_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uno_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uno_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB55_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB55_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uno_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+attributes #0 = { strictfp }
+
+declare i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(float, float, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(float, float, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
new file mode 100644
index 000000000000..6d53aff6f7a9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
@@ -0,0 +1,992 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X87-64
+
+define i32 @test_oeq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oeq_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB0_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB0_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB0_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oeq_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ogt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ogt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB1_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB1_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ogt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oge_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB2_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB2_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oge_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_olt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_olt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB3_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB3_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_olt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ole_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ole_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB4_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB4_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ole_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_one_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_one_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jne .LBB5_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB5_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_one_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ord_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ord_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jnp .LBB6_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB6_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ord_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ueq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ueq_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: je .LBB7_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB7_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ueq_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ugt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ugt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB8_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB8_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ugt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uge_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB9_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB9_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uge_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ult_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ult_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB10_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB10_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ult_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ule_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ule_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB11_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB11_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ule_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_une_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_une_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB12_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB12_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB12_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_une_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %esi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %edi, %eax
+; X87-64-NEXT: cmovpl %edi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uno_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uno_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jp .LBB13_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB13_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uno_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oeq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oeq_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB14_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB14_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB14_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oeq_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ogt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ogt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB15_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB15_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ogt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oge_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB16_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB16_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oge_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_olt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_olt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB17_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB17_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_olt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ole_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ole_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB18_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB18_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ole_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_one_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_one_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jne .LBB19_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB19_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_one_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ord_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ord_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jnp .LBB20_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB20_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ord_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ueq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ueq_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: je .LBB21_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB21_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ueq_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ugt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ugt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB22_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB22_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ugt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uge_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB23_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB23_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uge_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ult_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ult_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB24_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB24_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ult_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ule_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ule_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB25_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB25_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ule_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_une_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_une_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB26_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB26_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB26_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_une_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %esi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %edi, %eax
+; X87-64-NEXT: cmovpl %edi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uno_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uno_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jp .LBB27_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB27_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uno_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+attributes #0 = { strictfp }
+
+declare i1 @llvm.experimental.constrained.fcmp.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll
new file mode 100644
index 000000000000..56320aba1cbb
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <4 x i32> @test_v4f32_oeq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oeq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ogt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oge_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_olt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ole_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_one_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_one_q:
+; SSE: # %bb.0:
+; SSE: cmpneqps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ord_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ord_q:
+; SSE: # %bb.0:
+; SSE: cmpordps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ueq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ueq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: orps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ugt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uge_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ult_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ule_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_une_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_une_q:
+; SSE: # %bb.0:
+; SSE: cmpneqps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uno_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uno_q:
+; SSE: # %bb.0:
+; SSE: cmpunordps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @test_v2f64_oeq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oeq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ogt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oge_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_olt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ole_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_one_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_one_q:
+; SSE: # %bb.0:
+; SSE: cmpneqpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ord_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ord_q:
+; SSE: # %bb.0:
+; SSE: cmpordpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ueq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ueq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: orpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ugt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uge_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ult_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ule_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_une_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_une_q:
+; SSE: # %bb.0:
+; SSE: cmpneqpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uno_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uno_q:
+; SSE: # %bb.0:
+; SSE: cmpunordpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <4 x i32> @test_v4f32_oeq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oeq_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpeqps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_osps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ogt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ogt_s:
+; SSE: # %bb.0:
+; SSE: cmpltps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_oge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oge_s:
+; SSE: # %bb.0:
+; SSE: cmpleps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_olt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_olt_s:
+; SSE: # %bb.0:
+; SSE: cmpltps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ole_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ole_s:
+; SSE: # %bb.0:
+; SSE: cmpleps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_one_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_one_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE: cmpneqps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_osps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ord_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ord_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_sps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ueq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ueq_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE: cmpeqps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: orps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_usps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ugt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ugt_s:
+; SSE: # %bb.0:
+; SSE: cmpnleps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uge_s:
+; SSE: # %bb.0:
+; SSE: cmpnltps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ult_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ult_s:
+; SSE: # %bb.0:
+; SSE: cmpnleps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ule_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ule_s:
+; SSE: # %bb.0:
+; SSE: cmpnltps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_une_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_une_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpneqps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_usps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uno_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uno_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_sps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @test_v2f64_oeq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oeq_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpeqpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_ospd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ogt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ogt_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_oge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oge_s:
+; SSE: # %bb.0:
+; SSE: cmplepd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_olt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_olt_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ole_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ole_s:
+; SSE: # %bb.0:
+; SSE: cmplepd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_one_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_one_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE: cmpneqpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_ospd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ord_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ord_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_spd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ueq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ueq_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE: cmpeqpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: orpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uspd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ugt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ugt_s:
+; SSE: # %bb.0:
+; SSE: cmpnlepd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uge_s:
+; SSE: # %bb.0:
+; SSE: cmpnltpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ult_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ult_s:
+; SSE: # %bb.0:
+; SSE: cmpnlepd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ule_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ule_s:
+; SSE: # %bb.0:
+; SSE: cmpnltpd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_une_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_une_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpneqpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_uspd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uno_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uno_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_spd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float>, <4 x float>, metadata, metadata)
+declare <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double>, <2 x double>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float>, <4 x float>, metadata, metadata)
+declare <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double>, <2 x double>, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll
new file mode 100644
index 000000000000..c8aaa6af49ba
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll
@@ -0,0 +1,1243 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <8 x i32> @test_v8f32_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ogt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_oge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_olt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ole_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_one_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ord_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ueq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ugt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ult_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ule_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_une_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uno_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <4 x i64> @test_v4f64_oeq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ogt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_oge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_olt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ole_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_one_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ord_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ueq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ugt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ult_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ule_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_une_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uno_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <8 x i32> @test_v8f32_oeq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_osps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ogt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_oge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_olt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ole_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_one_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_osps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ord_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_sps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ueq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_usps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ugt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ult_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ule_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_une_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_usps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uno_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_sps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <4 x i64> @test_v4f64_oeq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_ospd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ogt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_oge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_olt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ole_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_one_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_ospd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ord_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_spd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ueq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uspd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ugt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ult_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ule_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_une_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_uspd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uno_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_spd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float>, <8 x float>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double>, <4 x double>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float>, <8 x float>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double>, <4 x double>, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll
new file mode 100644
index 000000000000..3671d1bb0401
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll
@@ -0,0 +1,961 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ogt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_oge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_olt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ole_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_one_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ord_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ueq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ugt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ult_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ule_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_une_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uno_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <8 x i64> @test_v8f64_oeq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ogt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_oge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_olt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ole_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_one_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ord_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ueq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ugt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ult_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ule_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_une_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uno_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <16 x i32> @test_v16f32_oeq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ogt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_oge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_olt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ole_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_one_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ord_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ueq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ugt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ult_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ule_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_une_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uno_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <8 x i64> @test_v8f64_oeq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ogt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_oge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_olt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ole_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_one_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ord_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ueq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ugt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ult_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ule_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_une_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uno_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)
+declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double>, <8 x double>, metadata, metadata)
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