[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

qshanz via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 9 18:13:18 PST 2019

Previous message: [PATCH] D70771: [NFC][PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules
Next message: [PATCH] D71002: [PowerPC] Exploitate the Vector Integer Average Instructions
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

steven.zhang added a comment.

@kparzysz Any more comments ? Thank you.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000

Previous message: [PATCH] D70771: [NFC][PowerPC] Replace the PPCISD:: SExtVElems with ISD::SIGN_EXTEND_INREG to leverage the combine rules
Next message: [PATCH] D71002: [PowerPC] Exploitate the Vector Integer Average Instructions
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list