[PATCH] D71138: [PowerPC] Fix %llvm.ppc.altivec.vc* lowering
Colin Samples via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 6 11:38:03 PST 2019
vddvss created this revision.
vddvss added reviewers: hfinkel, nemanjai, PowerPC.
Herald added subscribers: llvm-commits, shchenz, jsji, kbarton, hiraditya.
Herald added a project: LLVM.
r372285 changed LLVM to use a `TargetConstant` for parameters of intrinsics that are required to be immediates.
Since that commit, use of `%llvm.ppc.altivec.vc{fsx,fux,tsxs,tuxs}` intrinsics has not worked, and resulted in a `LLVM ERROR: Cannot select: intrinsic %llvm.ppc.altivec.vc*` error. The intrinsics' TableGen definitions matched on `imm` instead of `timm`.
This commit updates those definitions to use `timm`.
Fixes: http://llvm.org/44239
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D71138
Files:
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/test/CodeGen/PowerPC/pr44239.ll
Index: llvm/test/CodeGen/PowerPC/pr44239.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr44239.ll
@@ -0,0 +1,40 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -verify-machineinstrs < %s | FileCheck %s
+
+define <4 x float> @check_vcfsx(<4 x i32> %a) {
+entry:
+ %0 = tail call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> %a, i32 1)
+ ret <4 x float> %0
+; CHECK-LABEL: check_vcfsx
+; CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x float> @check_vcfux(<4 x i32> %a) {
+entry:
+ %0 = tail call <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32> %a, i32 1)
+ ret <4 x float> %0
+; CHECK-LABEL: check_vcfux
+; CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x i32> @check_vctsxs(<4 x float> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float> %a, i32 1)
+ ret <4 x i32> %0
+; CHECK-LABEL: check_vctsxs
+; CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+define <4 x i32> @check_vctuxs(<4 x float> %a) {
+entry:
+ %0 = tail call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> %a, i32 1)
+ ret <4 x i32> %0
+; CHECK-LABEL: check_vctuxs
+; CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 1
+}
+
+declare <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32>, i32 immarg)
+declare <4 x float> @llvm.ppc.altivec.vcfux(<4 x i32>, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vctsxs(<4 x float>, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float>, i32 immarg)
+
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -518,19 +518,19 @@
def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vcfsx $vD, $vB, $UIMM", IIC_VecFP,
[(set v4f32:$vD,
- (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
+ (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>;
def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vcfux $vD, $vB, $UIMM", IIC_VecFP,
[(set v4f32:$vD,
- (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
+ (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>;
def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vctsxs $vD, $vB, $UIMM", IIC_VecFP,
[(set v4i32:$vD,
- (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
+ (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>;
def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vctuxs $vD, $vB, $UIMM", IIC_VecFP,
[(set v4i32:$vD,
- (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
+ (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>;
// Defines with the UIM field set to 0 for floating-point
// to integer (fp_to_sint/fp_to_uint) conversions and integer
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