[llvm] 3fab427 - [ARM][MVE] Fix copy-paste error in VQSHL instruction ids.

[Simon Tatham via llvm-commits]

Author: Simon Tatham
Date: 2019-12-06T15:23:23Z
New Revision: 3fab4276cbf1a57f049428145d4c9a0d9bcfa82c

URL: https://github.com/llvm/llvm-project/commit/3fab4276cbf1a57f049428145d4c9a0d9bcfa82c
DIFF: https://github.com/llvm/llvm-project/commit/3fab4276cbf1a57f049428145d4c9a0d9bcfa82c.diff

LOG: [ARM][MVE] Fix copy-paste error in VQSHL instruction ids.

Summary:
The immediate forms of the MVE VQSHL instruction have MC names like
`MVE_VSLIimms8` and `MVE_VSLIimmu32`. Those names are confusing,
because VSLI is a completely different shift instruction with no
semantic relation to VQSHL. But it just happens to be defined
immediately before VQSHL in `ARMInstrMVE.td`, so this looks like a
copy-paste error. Renamed the ids to match the instruction name.

Reviewers: ostannard, dmgreen, MarkMurrayARM, miyuki

Reviewed By: miyuki

Subscribers: kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71114

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrMVE.td
    llvm/unittests/Target/ARM/MachineInstrTest.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index c81e60b3360a..3c0499ac4908 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -2529,32 +2529,32 @@ class MVE_VQSHL_imm<string suffix, dag imm>
   let Inst{10-8} = 0b111;
 }
 
-def MVE_VSLIimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
+def MVE_VQSHLimms8 : MVE_VQSHL_imm<"s8", (ins imm0_7:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21-19} = 0b001;
 }
 
-def MVE_VSLIimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
+def MVE_VQSHLimmu8 : MVE_VQSHL_imm<"u8", (ins imm0_7:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21-19} = 0b001;
 }
 
-def MVE_VSLIimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
+def MVE_VQSHLimms16 : MVE_VQSHL_imm<"s16", (ins imm0_15:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21-20} = 0b01;
 }
 
-def MVE_VSLIimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
+def MVE_VQSHLimmu16 : MVE_VQSHL_imm<"u16", (ins imm0_15:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21-20} = 0b01;
 }
 
-def MVE_VSLIimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
+def MVE_VQSHLimms32 : MVE_VQSHL_imm<"s32", (ins imm0_31:$imm)> {
   let Inst{28} = 0b0;
   let Inst{21} = 0b1;
 }
 
-def MVE_VSLIimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
+def MVE_VQSHLimmu32 : MVE_VQSHL_imm<"u32", (ins imm0_31:$imm)> {
   let Inst{28} = 0b1;
   let Inst{21} = 0b1;
 }

diff  --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
index 8ca864aa8c63..fc7dc9e67ca5 100644
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -327,6 +327,12 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VQSHLU_imms16:
     case MVE_VQSHLU_imms32:
     case MVE_VQSHLU_imms8:
+    case MVE_VQSHLimms16:
+    case MVE_VQSHLimms32:
+    case MVE_VQSHLimms8:
+    case MVE_VQSHLimmu16:
+    case MVE_VQSHLimmu32:
+    case MVE_VQSHLimmu8:
     case MVE_VQSHL_by_vecs16:
     case MVE_VQSHL_by_vecs32:
     case MVE_VQSHL_by_vecs8:
@@ -411,12 +417,6 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
     case MVE_VSLIimm16:
     case MVE_VSLIimm32:
     case MVE_VSLIimm8:
-    case MVE_VSLIimms16:	
-    case MVE_VSLIimms32:
-    case MVE_VSLIimms8:
-    case MVE_VSLIimmu16:
-    case MVE_VSLIimmu32:
-    case MVE_VSLIimmu8:
     case MVE_VSRIimm16:
     case MVE_VSRIimm32:
     case MVE_VSRIimm8: