[PATCH] D69484: [PowerPC] Relax the restrictions on loading doubles with SPE

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp requested changes to this revision.
stefanp added a comment.
This revision now requires changes to proceed.

Please add a test case for this.
Maybe an test were we have an SPE load of f64 with a 8 bit offset and one where the offset is larger or perhaps not aligned.  Anyway, that's just a suggestion. You probably have a better idea of what you would like to test for this.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:2281
+            && !(imm % EVXEncodingAlignment))
+          return false; // Offset is okay for the 8-bit index
+        Base = N.getOperand(0);
----------------
This section of code looks to be loop invariant. I'm not sure if the intention was to use `UT` or not but if it is invariant you can pull it out of the loop. Basically, if `isIntU8Immediate(N.getOperand(1), imm)  && !(imm % EVXEncodingAlignment)` is true then the function can only return false.


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  https://reviews.llvm.org/D69484/new/

https://reviews.llvm.org/D69484