[PATCH] D70431: [DebugInfo] Make describeLoadedValue() reg aware

[Vedant Kumar via Phabricator via llvm-commits]

vsk added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:5356
+
+  if (Reg != MI.getOperand(0).getReg())
+    return None;
----------------
Probably worth adding a comment here similar to the ones elsewhere, about cases where the add defines a super/sub register of the described reg not being supported yet.


================
Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:7707
+    Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {});
+    if (X86MCRegisterClasses[X86::GR64RegClassID].contains(Reg))
+      Expr = DIExpression::appendExt(Expr, 32, 64, true);
----------------
IIUC, at this point, `Reg` must be a sub-register of operand 0 or equal to it. Can operand 0 of a MOVSX64rr32 ever not be 64-bit, and if not, is this check necessary?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70431/new/

https://reviews.llvm.org/D70431