[PATCH] D69486: PowerPC: Fix SPE f64 VAARG handling.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp added a comment.

I think that for `f64` on SPE the `GprIndex` you are computing it going to be ignored. (See my comment...)

Also, would it be possible to add a test case to go with it?



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:3099
   // select overflow_area if index > 8
   SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
                             DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
----------------
You are computing a new `GprIndex` above for `MVT::f64` on SPE.
However, down here you don't use the newly computed `GprIndex` because `VT.isInteger()` is going to return false so you are going to get `FprIndex` instead. 
The same thing happens later on in this function where we use `VT.isInteger() ? GprIndex : FprIndex` again. 
It looks like the newly computed `GprIndex` is not going to be used since you are always going to be getting `FprIndex` when you have `MVT::f64`. 


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https://reviews.llvm.org/D69486