[llvm] f0355bc - [AArch64][SVE] Implement element count intrinsics
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 5 02:27:50 PST 2019
Author: Cullen Rhodes
Date: 2019-12-05T10:26:49Z
New Revision: f0355bc4d15121cd89c7b6d8fce52c192019b3ab
URL: https://github.com/llvm/llvm-project/commit/f0355bc4d15121cd89c7b6d8fce52c192019b3ab
DIFF: https://github.com/llvm/llvm-project/commit/f0355bc4d15121cd89c7b6d8fce52c192019b3ab.diff
LOG: [AArch64][SVE] Implement element count intrinsics
Summary:
Adds intrinsics for the following:
* cntb
* cnth
* cntw
* cntd
* cntp
Reviewers: sdesmalen, huntergr, dancgr, rengolin, efriedma, rovka
Reviewed By: efriedma
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70967
Added:
llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
Modified:
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 0f6b9532cfca..1edce65c9ce6 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -927,6 +927,16 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
LLVMVectorOfBitcastsToInt<0>],
[IntrNoMem]>;
+ class AdvSIMD_SVE_CNTB_Intrinsic
+ : Intrinsic<[llvm_i64_ty],
+ [llvm_i32_ty],
+ [IntrNoMem]>;
+
+ class AdvSIMD_SVE_CNTP_Intrinsic
+ : Intrinsic<[llvm_i64_ty],
+ [llvm_anyvector_ty, LLVMMatchType<0>],
+ [IntrNoMem]>;
+
class AdvSIMD_SVE_DOT_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
@@ -1060,6 +1070,17 @@ def int_aarch64_sve_cls : AdvSIMD_Merged1VectorArg_Intrinsic;
def int_aarch64_sve_clz : AdvSIMD_Merged1VectorArg_Intrinsic;
def int_aarch64_sve_cnt : AdvSIMD_SVE_CNT_Intrinsic;
+//
+// Counting elements
+//
+
+def int_aarch64_sve_cntb : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cnth : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cntw : AdvSIMD_SVE_CNTB_Intrinsic;
+def int_aarch64_sve_cntd : AdvSIMD_SVE_CNTB_Intrinsic;
+
+def int_aarch64_sve_cntp : AdvSIMD_SVE_CNTP_Intrinsic;
+
//
// Reversal
//
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index b547833b154b..c75208e4aaca 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -788,11 +788,11 @@ let Predicates = [HasSVE] in {
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
- defm CNTB_XPiI : sve_int_count<0b000, "cntb">;
- defm CNTH_XPiI : sve_int_count<0b010, "cnth">;
- defm CNTW_XPiI : sve_int_count<0b100, "cntw">;
- defm CNTD_XPiI : sve_int_count<0b110, "cntd">;
- defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp">;
+ defm CNTB_XPiI : sve_int_count<0b000, "cntb", int_aarch64_sve_cntb>;
+ defm CNTH_XPiI : sve_int_count<0b010, "cnth", int_aarch64_sve_cnth>;
+ defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>;
+ defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>;
+ defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>;
defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">;
defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 23364f239aed..96a0117c9551 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -504,11 +504,17 @@ class sve_int_pcount_pred<bits<2> sz8_64, bits<4> opc, string asm,
let Inst{4-0} = Rd;
}
-multiclass sve_int_pcount_pred<bits<4> opc, string asm> {
+multiclass sve_int_pcount_pred<bits<4> opc, string asm,
+ SDPatternOperator int_op> {
def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>;
def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>;
def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>;
+
+ def : SVE_2_Op_Pat<i64, int_op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
+ def : SVE_2_Op_Pat<i64, int_op, nxv8i1, nxv8i1, !cast<Instruction>(NAME # _H)>;
+ def : SVE_2_Op_Pat<i64, int_op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>;
+ def : SVE_2_Op_Pat<i64, int_op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>;
}
//===----------------------------------------------------------------------===//
@@ -533,13 +539,16 @@ class sve_int_count<bits<3> opc, string asm>
let Inst{4-0} = Rd;
}
-multiclass sve_int_count<bits<3> opc, string asm> {
+multiclass sve_int_count<bits<3> opc, string asm, SDPatternOperator op> {
def NAME : sve_int_count<opc, asm>;
def : InstAlias<asm # "\t$Rd, $pattern",
(!cast<Instruction>(NAME) GPR64:$Rd, sve_pred_enum:$pattern, 1), 1>;
def : InstAlias<asm # "\t$Rd",
(!cast<Instruction>(NAME) GPR64:$Rd, 0b11111, 1), 2>;
+
+ def : Pat<(i64 (op sve_pred_enum:$pattern)),
+ (!cast<Instruction>(NAME) sve_pred_enum:$pattern, 1)>;
}
class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
new file mode 100644
index 000000000000..a3fd4faf196f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
@@ -0,0 +1,99 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; CNTB
+;
+
+define i64 @cntb() {
+; CHECK-LABEL: cntb:
+; CHECK: cntb x0, vl2
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntb(i32 2)
+ ret i64 %out
+}
+
+;
+; CNTH
+;
+
+define i64 @cnth() {
+; CHECK-LABEL: cnth:
+; CHECK: cnth x0, vl3
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cnth(i32 3)
+ ret i64 %out
+}
+
+;
+; CNTW
+;
+
+define i64 @cntw() {
+; CHECK-LABEL: cntw:
+; CHECK: cntw x0, vl4
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntw(i32 4)
+ ret i64 %out
+}
+
+;
+; CNTD
+;
+
+define i64 @cntd() {
+; CHECK-LABEL: cntd:
+; CHECK: cntd x0, vl5
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntd(i32 5)
+ ret i64 %out
+}
+
+;
+; CNTP
+;
+
+define i64 @cntp_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: cntp_b8:
+; CHECK: cntp x0, p0, p1.b
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %pg,
+ <vscale x 16 x i1> %a)
+ ret i64 %out
+}
+
+define i64 @cntp_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
+; CHECK-LABEL: cntp_b16:
+; CHECK: cntp x0, p0, p1.h
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %pg,
+ <vscale x 8 x i1> %a)
+ ret i64 %out
+}
+
+define i64 @cntp_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
+; CHECK-LABEL: cntp_b32:
+; CHECK: cntp x0, p0, p1.s
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %pg,
+ <vscale x 4 x i1> %a)
+ ret i64 %out
+}
+
+define i64 @cntp_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
+; CHECK-LABEL: cntp_b64:
+; CHECK: cntp x0, p0, p1.d
+; CHECK-NEXT: ret
+ %out = call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %pg,
+ <vscale x 2 x i1> %a)
+ ret i64 %out
+}
+
+declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
+declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)
+
+declare i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
+declare i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
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