[PATCH] D69836: [MIR] Target specific MIR formating and parsing
Peng Guo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 4 15:36:09 PST 2019
pguo updated this revision to Diff 232228.
pguo added a comment.
- [MIR] Target specific MIR formatting and parsing
Use Optional for OpIdx argument.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D69836/new/
https://reviews.llvm.org/D69836
Files:
llvm/include/llvm/CodeGen/MIRFormatter.h
llvm/include/llvm/CodeGen/MIRParser/MIParser.h
llvm/include/llvm/CodeGen/MachineMemOperand.h
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/include/llvm/CodeGen/PseudoSourceValue.h
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/include/llvm/Target/TargetMachine.h
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/CodeGen/MIRParser/MILexer.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/Target/TargetMachine.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.load.1d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.image.sample.1d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.load.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.buffer.store.ll
llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
llvm/unittests/CodeGen/MachineOperandTest.cpp
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