[PATCH] D71009: [AArch64][SVE] Add wide compare immediate patterns

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10507
+  if (Comparator.getOpcode() == AArch64ISD::DUP ||
+      Comparator.getOpcode() == ISD::SPLAT_VECTOR) {
+    unsigned IID = getIntrinsicID(N);
----------------
I guess it's sort of orthogonal to this patch, but why do we have two opcodes for the same operation?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10553
+      if (auto *CN = dyn_cast<ConstantSDNode>(Comparator.getOperand(0))) {
+        uint64_t ImmVal = CN->getZExtValue();
+
----------------
Do we actually know we're dealing with a legal type, at this point?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71009/new/

https://reviews.llvm.org/D71009