[PATCH] D70680: [ARM][Thumb2] Fix ADD/SUB invalid writes to SP

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:925-938
+    bits<4>  Rn = 13;
+    bits<4>  Rd = 13;
+    bits<12> imm;
+
+    let Inst{31-27} = 0b11110;
+    let Inst{26}    = imm{11};
+    let Inst{25-24} = 0b01;
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This duplicates a lot of what's in T2sTwoRegImm, and also incorrectly forces bit 20 (which encodes the 's' bit) to 0 causing adds to be encoded as add.

I think what should be here is the same as the ri variant, but with "let Rn = 13; let Rd = 13;" at the top.


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Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:987
+       let Inst{23-21} = op23_21;
+       let Inst{20} = 0;
+       let Inst{19-16} = Rn;
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Should comment that this is the S bit, for consistency with ri12 variant above.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70680/new/

https://reviews.llvm.org/D70680