[PATCH] D70874: [X86] Add initialization of MXCSR in llvm-exegesis
Pengfei Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 3 17:24:09 PST 2019
pengfei added a comment.
> Please note that currently we only state the rounding modes and the IEEE masks bits of MXCSR. This means instructions like VRSQRT14PS, which only have dependence on FTZ and DAZ, wouldn't be modeled.
FTZ and DAZ are modeled now by commit rGc8995de06994 <https://reviews.llvm.org/rGc8995de06994c40ff2505bd18321fab8b4dc41be>. Thanks.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70874/new/
https://reviews.llvm.org/D70874
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