[PATCH] D69936: [IPRA][ARM] Spill extra registers at -Oz

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

Looks reasonable (haven't looked at the ARM part.)
The change in shrink wrapping doesn't look correct to me though. Is that particular change require?



================
Comment at: llvm/lib/CodeGen/MachineRegisterInfo.cpp:629
 
-    IsUpdatedCSRsInitialized = true;
-  }
+void MachineRegisterInfo::disableCalleeSavedRegister(unsigned Reg) {
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
----------------
Could you change unsigned to Register here and in `enableCalleeSavedRegister ` while you are at it?
Fine as a follow-up commit or a preparatory commit :).


================
Comment at: llvm/lib/CodeGen/ShrinkWrap.cpp:170
 
-      TFI->determineCalleeSaves(*MachineFunc, SavedRegs, RS);
+      TFI->getCalleeSaves(*MachineFunc, SavedRegs);
 
----------------
That change doesn't look right.


================
Comment at: llvm/test/CodeGen/ARM/ipra-extra-spills-shrink-wrapping.mir:36
+  }
+...
+---
----------------
You should be able to remove the section with the LLVM IR.
Just make sure to remove the LLVM IR basic block names in the names of the MachineBasicBlock.
E.g.,   bb.0.entry: =>   bb.0:


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D69936/new/

https://reviews.llvm.org/D69936