[PATCH] D70806: [Aarch64][SVE] Add intrinsics for gather loads (vector + imm)

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar updated this revision to Diff 231713.
andwar added a comment.

- Reverted one incorrect (introduced by mistake) change in a TableGen pattern ( `uimm5s2` vs `uimm5s4`)
- Created a TableGen class for the intrinsics introduced here - for consistency with the other patches for gather loads


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70806/new/

https://reviews.llvm.org/D70806

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

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