[PATCH] D70896: AMDGPU: Avoid folding 2 constant operands into an SALU operation
David Stuttard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 2 05:06:52 PST 2019
dstuttard created this revision.
Herald added subscribers: llvm-commits, hiraditya, t-tye, tpr, yaxunl, nhaehnle, wdng, jvesely, kzhuravl, arsenm.
Herald added a project: LLVM.
Catch the (admittedly unusual) case where SIFoldOperands attempts to fold 2
constant operands into the same SALU operation, with neither operand able to be
encoded as an inline constant.
Change-Id: Ibc48d662c9ffd8bbacd154976b0b1c257ace0927
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D70896
Files:
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
Index: llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/fold-sgpr-multi-imm.mir
@@ -0,0 +1,25 @@
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s
+
+# GCN-LABEL: name: test_part_fold{{$}}
+# GCN: %2:sreg_32 = S_ADD_I32 70, %1
+---
+name: test_part_fold
+tracksRegLiveness: true
+body: |
+ bb.0:
+ %0:sreg_32 = S_MOV_B32 70
+ %1:sreg_32 = S_MOV_B32 80
+ %2:sreg_32 = S_ADD_I32 %0, %1, implicit-def $scc
+...
+
+# GCN-LABEL: name: test_inline_const{{$}}
+# GCN: %2:sreg_32 = S_ADD_I32 70, 63
+---
+name: test_inline_const
+tracksRegLiveness: true
+body: |
+ bb.0:
+ %0:sreg_32 = S_MOV_B32 70
+ %1:sreg_32 = S_MOV_B32 63
+ %2:sreg_32 = S_ADD_I32 %0, %1, implicit-def $scc
+...
Index: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -429,6 +429,26 @@
return true;
}
+ // Check the case where we might introduce a second constant operand to a scalar instruction
+ if (TII->isSALU(MI->getOpcode())) {
+ const MCInstrDesc &InstDesc = MI->getDesc();
+ const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
+ const SIRegisterInfo &TRI = TII->getRegisterInfo();
+
+ // Fine if the operand can be encoded as an inline constant
+ if (!(OpToFold->isImm() && TII->isInlineConstant(*OpToFold, OpInfo) &&
+ TRI.opCanUseInlineConstant(OpInfo.OperandType))) {
+ // Otherwise check for another constant
+ for (unsigned i = 0, e = InstDesc.getNumOperands(); i != e; ++i) {
+ auto &Op = MI->getOperand(i);
+ if (OpNo != i && !Op.isReg() &&
+ Op.isImm() && !TII->isInlineConstant(Op, OpInfo)) {
+ return false;
+ }
+ }
+ }
+ }
+
appendFoldCandidate(FoldList, MI, OpNo, OpToFold);
return true;
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70896.231680.patch
Type: text/x-patch
Size: 2030 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191202/05f3591a/attachment.bin>
More information about the llvm-commits
mailing list