[PATCH] D70891: [X86] Add initialization of FPCW in llvm-exegesis

[Pengfei Wang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG76b70f6f75e9: [X86] Add initialization of FPCW in llvm-exegesis (authored by pengfei).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70891/new/

https://reviews.llvm.org/D70891

Files:
  llvm/test/tools/llvm-exegesis/X86/uops-ADD_F32m.s
  llvm/tools/llvm-exegesis/lib/X86/Target.cpp


Index: llvm/tools/llvm-exegesis/lib/X86/Target.cpp
===================================================================
--- llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -439,7 +439,8 @@
 
   std::vector<MCInst> popFlagAndFinalize();
 
-  std::vector<MCInst> loadMXCSRAndFinalize(bool HasAVX);
+  std::vector<MCInst> loadImplicitRegAndFinalize(unsigned Opcode,
+                                                 unsigned Value);
 
 private:
   ConstantInliner &add(const MCInst &Inst) {
@@ -501,10 +502,11 @@
   return std::move(Instructions);
 }
 
-std::vector<MCInst> ConstantInliner::loadMXCSRAndFinalize(bool HasAVX) {
+std::vector<MCInst>
+ConstantInliner::loadImplicitRegAndFinalize(unsigned Opcode, unsigned Value) {
   add(allocateStackSpace(4));
-  add(fillStackSpace(X86::MOV32mi, 0, 0x1f80)); // Mask all FP exceptions
-  add(MCInstBuilder(HasAVX ? X86::VLDMXCSR : X86::LDMXCSR)
+  add(fillStackSpace(X86::MOV32mi, 0, Value)); // Mask all FP exceptions
+  add(MCInstBuilder(Opcode)
           // Address = ESP
           .addReg(X86::RSP) // BaseReg
           .addImm(1)        // ScaleAmt
@@ -715,7 +717,11 @@
   if (Reg == X86::EFLAGS)
     return CI.popFlagAndFinalize();
   if (Reg == X86::MXCSR)
-    return CI.loadMXCSRAndFinalize(STI.getFeatureBits()[X86::FeatureAVX]);
+    return CI.loadImplicitRegAndFinalize(
+              STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR
+                                                    : X86::LDMXCSR, 0x1f80);
+  if (Reg == X86::FPCW)
+    return CI.loadImplicitRegAndFinalize(X86::FLDCW16m, 0x37f);
   return {}; // Not yet implemented.
 }
 
Index: llvm/test/tools/llvm-exegesis/X86/uops-ADD_F32m.s
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-exegesis/X86/uops-ADD_F32m.s
@@ -0,0 +1,9 @@
+# RUN: llvm-exegesis -mode=uops -opcode-name=ADD_F32m -repetition-mode=duplicate | FileCheck %s
+# RUN: llvm-exegesis -mode=uops -opcode-name=ADD_F32m -repetition-mode=loop | FileCheck %s
+
+CHECK:      mode:            uops
+CHECK-NEXT: key:
+CHECK-NEXT:   instructions:
+CHECK-NEXT:     ADD_F32m
+CHECK:      register_initial_values:
+CHECK:      FPCW


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