[PATCH] D70795: [AArch64][SVE] Add intrinsics and patterns for logical predicate instructions
Sander de Smalen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 29 08:35:13 PST 2019
sdesmalen added a comment.
Other than the two nits, LGTM otherwise.
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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:997
+def int_aarch64_sve_bic : AdvSIMD_2VectorArg_Intrinsic;
+def int_aarch64_sve_bic_pred : AdvSIMD_Pred2VectorArg_Intrinsic;
+
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Can you also swap these two (`bic` and `bic_pred`)? That makes that naming consistent with the others.
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Comment at: llvm/test/CodeGen/AArch64/sve-pred-log.ll:50
+ %res = call <vscale x 8 x i1> @llvm.aarch64.sve.and.nxv8i1(<vscale x 8 x i1> %Pg,
+ <vscale x 8 x i1> %Pn,
+ <vscale x 8 x i1> %Pd)
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nit: is this indentation on purpose?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70795/new/
https://reviews.llvm.org/D70795
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