[PATCH] D70812: [Aarch64][SVE] Add DAG combine rules for gather loads and sext/zext

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar created this revision.
andwar added reviewers: sdesmalen, huntergr, kmclaughlin, efriedma, rengolin, rovka, dancgr, mgudim.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

These changes allow us to support sign-extending gather loads with the  existing intrinsics (i.e. @llvm.aarch64.sve.ld1.gather.*).


https://reviews.llvm.org/D70812

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-scaled-32bit-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-unscaled-32bit-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base.ll

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