[PATCH] D70431: [DebugInfo] Make describeLoadedValue() reg aware

[David Stenberg via Phabricator via llvm-commits]

dstenb updated this revision to Diff 231254.
dstenb added a comment.
Herald added a subscriber: ormris.

Update the patch. Sorry for the delay!

This moves the sub- and super-register handling out of TargetInstrInfo's `describeLoadedValue()` implementation, and leaves it up to each target to override cases where that can occur. For copy instructions there are asserts, so that we can catch such cases.

To move the sub- and super-register handling out for add immediate instructions, this changes that hook so that it takes a register that it should describe. Since we may want to return a sub- or super-register, the return value is changed from a MachineOperand pointer to a plain Register. Since I'm not very familiar with AArch64, nor have a machine to test that, I did not dare to describe such cases.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70431/new/

https://reviews.llvm.org/D70431

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir

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