[PATCH] D70783: AMDGPU: Fixed indeterminate map iteration in SIPeepholeSDWA

Tim Renouf via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Nov 27 11:51:38 PST 2019


tpr updated this revision to Diff 231305.
tpr added a comment.

V2: Sorted includes alphabetically.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70783/new/

https://reviews.llvm.org/D70783

Files:
  llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp


Index: llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
+++ llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
@@ -26,6 +26,7 @@
 #include "SIRegisterInfo.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "Utils/AMDGPUBaseInfo.h"
+#include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/None.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/STLExtras.h"
@@ -73,8 +74,8 @@
   const SIRegisterInfo *TRI;
   const SIInstrInfo *TII;
 
-  std::unordered_map<MachineInstr *, std::unique_ptr<SDWAOperand>> SDWAOperands;
-  std::unordered_map<MachineInstr *, SDWAOperandsVector> PotentialMatches;
+  MapVector<MachineInstr *, std::unique_ptr<SDWAOperand>> SDWAOperands;
+  MapVector<MachineInstr *, SDWAOperandsVector> PotentialMatches;
   SmallVector<MachineInstr *, 8> ConvertedInstructions;
 
   Optional<int64_t> foldToImm(const MachineOperand &Op) const;


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