[PATCH] D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets

[Andrzej Warzynski via Phabricator via llvm-commits]

andwar created this revision.
andwar added reviewers: sdesmalen, kmclaughlin, eli.friedman, rengolin, rovka, huntergr, dancgr, mgudim.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: LLVM.

This patch adds intrinsics for SVE gather loads for which the offsets are 32-bits wide and are:

- unscaled
  - @llvm.aarch64.sve.ld1.gather.sxtw
  - @llvm.aarch64.sve.ld1.gather.uxtw
- scaled (offsets become indices)
  - @llvm.arch64.sve.ld1.gather.sxtw.index
    - @llvm.arch64.sve.ld1.gather.uxtw.index

The offsets are either zero (uxtw) or sign (sxtw) extended to 64 bits.

These intrinsics map 1-1 to the corresponding SVE instructions (examples for half-words):

- unscaled
  - ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
    - ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
- scaled
  - ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
  - ld1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70782

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-scaled-32bit-offsets.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-unscaled-32bit-offsets.ll

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