[llvm] 3ec193f - [SystemZ] Don't build a PPA instruction with an immediate 0 operand.

[Jonas Paulsson via llvm-commits]

Author: Jonas Paulsson
Date: 2019-11-26T11:21:01+01:00
New Revision: 3ec193fb527e697faac4ef8f30934dd7bce849a7

URL: https://github.com/llvm/llvm-project/commit/3ec193fb527e697faac4ef8f30934dd7bce849a7
DIFF: https://github.com/llvm/llvm-project/commit/3ec193fb527e697faac4ef8f30934dd7bce849a7.diff

LOG: [SystemZ]  Don't build a PPA instruction with an immediate 0 operand.

The improvement in the machine verifier for operand types (D63973) discovered
a bad operand in a test using a PPA instruction. It was an immediate 0 where
a register was expected.

This patch fixes this (NFC) by now making the PPA second register operand
NoRegister instead of a zero immediate in the MIR.

Review: Ulrich Weigand
https://reviews.llvm.org/D70501

Added: 
    

Modified: 
    llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
    llvm/lib/Target/SystemZ/SystemZInstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
index 91cb35dd72f2..c5cce39747a9 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.cpp
@@ -41,8 +41,12 @@ void SystemZInstPrinter::printAddress(unsigned Base, int64_t Disp,
 
 void SystemZInstPrinter::printOperand(const MCOperand &MO, const MCAsmInfo *MAI,
                                       raw_ostream &O) {
-  if (MO.isReg())
-    O << '%' << getRegisterName(MO.getReg());
+  if (MO.isReg()) {
+    if (!MO.getReg())
+      O << '0';
+    else
+      O << '%' << getRegisterName(MO.getReg());
+  }
   else if (MO.isImm())
     O << MO.getImm();
   else if (MO.isExpr())

diff  --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 8b334756611a..041971ca7cb8 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -2069,7 +2069,7 @@ let Predicates = [FeatureProcessorAssist] in {
     def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>;
   def : Pat<(int_s390_ppa_txassist GR32:$src),
             (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
-                 0, 1)>;
+                 zero_reg, 1)>;
 }
 
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