[llvm] cced971 - [ARM][ReachingDefs] RDA in LoLoops
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 26 02:14:19 PST 2019
Author: Sam Parker
Date: 2019-11-26T10:13:46Z
New Revision: cced971fd3d6713ec4989990e1b2f42c8539f0f3
URL: https://github.com/llvm/llvm-project/commit/cced971fd3d6713ec4989990e1b2f42c8539f0f3
DIFF: https://github.com/llvm/llvm-project/commit/cced971fd3d6713ec4989990e1b2f42c8539f0f3.diff
LOG: [ARM][ReachingDefs] RDA in LoLoops
Add several new methods to ReachingDefAnalysis:
- getReachingMIDef, instead of returning an integer, return the
MachineInstr that produces the def.
- getInstFromId, return a MachineInstr for which the given integer
corresponds to.
- hasSameReachingDef, return whether two MachineInstr use the same
def of a register.
- isRegUsedAfter, return whether a register is used after a given
MachineInstr.
These methods have been used in ARMLowOverhead to replace searching
for uses/defs.
Differential Revision: https://reviews.llvm.org/D70009
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
Modified:
llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/ARM/O3-pipeline.ll
llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
index 9ab9e8068eab..dda82b7717e7 100644
--- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
+++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h
@@ -87,13 +87,29 @@ class ReachingDefAnalysis : public MachineFunctionPass {
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ MachineFunctionProperties::Property::NoVRegs).set(
+ MachineFunctionProperties::Property::TracksLiveness);
}
/// Provides the instruction id of the closest reaching def instruction of
/// PhysReg that reaches MI, relative to the begining of MI's basic block.
int getReachingDef(MachineInstr *MI, int PhysReg);
+ /// Provides the instruction of the closest reaching def instruction of
+ /// PhysReg that reaches MI, relative to the begining of MI's basic block.
+ MachineInstr *getReachingMIDef(MachineInstr *MI, int PhysReg);
+
+ /// Provides the MI, from the given block, corresponding to the Id or a
+ /// nullptr if the id does not refer to the block.
+ MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId);
+
+ /// Return whether A and B use the same def of PhysReg.
+ bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg);
+
+ /// Return whether the given register is used after MI, whether it's a local
+ /// use or a live out.
+ bool isRegUsedAfter(MachineInstr *MI, int PhysReg);
+
/// Provides the clearance - the number of instructions since the closest
/// reaching def instuction of PhysReg that reaches MI.
int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index 2850033e6419..55d9cb65999c 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
@@ -189,7 +190,58 @@ int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
return LatestDef;
}
+MachineInstr* ReachingDefAnalysis::getReachingMIDef(MachineInstr *MI, int PhysReg) {
+ return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg));
+}
+
+MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB,
+ int InstId) {
+ assert(MBB->getNumber() < MBBReachingDefs.size() &&
+ "Unexpected basic block number.");
+ assert(InstId < static_cast<int>(MBB->size()) &&
+ "Unexpected instruction id.");
+
+ if (InstId < 0)
+ return nullptr;
+
+ for (auto &MI : *MBB) {
+ if (InstIds.count(&MI) && InstIds[&MI] == InstId)
+ return &MI;
+ }
+ return nullptr;
+}
+
int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {
assert(InstIds.count(MI) && "Unexpected machine instuction.");
return InstIds[MI] - getReachingDef(MI, PhysReg);
}
+
+bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B,
+ int PhysReg) {
+ MachineBasicBlock *ParentA = A->getParent();
+ MachineBasicBlock *ParentB = B->getParent();
+ if (ParentA != ParentB)
+ return false;
+
+ return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg);
+}
+
+bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) {
+ MachineBasicBlock *MBB = MI->getParent();
+ LivePhysRegs LiveRegs(*TRI);
+ LiveRegs.addLiveOuts(*MBB);
+
+ // Yes if the register is live out of the basic block.
+ if (LiveRegs.contains(PhysReg))
+ return true;
+
+ // Walk backwards through the block to see if the register is live at some
+ // point.
+ for (auto Last = MBB->rbegin(), End = MBB->rend(); Last != End; ++Last) {
+ LiveRegs.stepBackward(*Last);
+ if (LiveRegs.contains(PhysReg))
+ return InstIds[&*Last] > InstIds[MI];
+ }
+ return false;
+}
+
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 733a3f166069..7487a43b7aa3 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -25,6 +25,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"
using namespace llvm;
@@ -104,10 +106,11 @@ namespace {
// Is it safe to define LR with DLS/WLS?
// LR can be defined if it is the operand to start, because it's the same
// value, or if it's going to be equivalent to the operand to Start.
- MachineInstr *IsSafeToDefineLR();
+ MachineInstr *IsSafeToDefineLR(ReachingDefAnalysis *RDA);
- // Check the branch targets are within range and we satisfy our restructi
- void CheckLegality(ARMBasicBlockUtils *BBUtils);
+ // Check the branch targets are within range and we satisfy our
+ // restrictions.
+ void CheckLegality(ARMBasicBlockUtils *BBUtils, ReachingDefAnalysis *RDA);
bool FoundAllComponents() const {
return Start && Dec && End;
@@ -127,6 +130,7 @@ namespace {
class ARMLowOverheadLoops : public MachineFunctionPass {
MachineFunction *MF = nullptr;
+ ReachingDefAnalysis *RDA = nullptr;
const ARMBaseInstrInfo *TII = nullptr;
MachineRegisterInfo *MRI = nullptr;
std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
@@ -139,6 +143,7 @@ namespace {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
AU.addRequired<MachineLoopInfo>();
+ AU.addRequired<ReachingDefAnalysis>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -146,7 +151,8 @@ namespace {
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoVRegs);
+ MachineFunctionProperties::Property::NoVRegs).set(
+ MachineFunctionProperties::Property::TracksLiveness);
}
StringRef getPassName() const override {
@@ -183,31 +189,6 @@ static bool IsLoopStart(MachineInstr &MI) {
MI.getOpcode() == ARM::t2WhileLoopStart;
}
-template<typename T>
-static MachineInstr* SearchForDef(MachineInstr *Begin, T End, unsigned Reg) {
- for(auto &MI : make_range(T(Begin), End)) {
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
- continue;
- return &MI;
- }
- }
- return nullptr;
-}
-
-static MachineInstr* SearchForUse(MachineInstr *Begin,
- MachineBasicBlock::iterator End,
- unsigned Reg) {
- for(auto &MI : make_range(MachineBasicBlock::iterator(Begin), End)) {
- for (auto &MO : MI.operands()) {
- if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
- continue;
- return &MI;
- }
- }
- return nullptr;
-}
-
static bool IsVCTP(MachineInstr *MI) {
switch (MI->getOpcode()) {
default:
@@ -221,73 +202,41 @@ static bool IsVCTP(MachineInstr *MI) {
return false;
}
-MachineInstr *LowOverheadLoop::IsSafeToDefineLR() {
+MachineInstr *LowOverheadLoop::IsSafeToDefineLR(ReachingDefAnalysis *RDA) {
+ // We can define LR because LR already contains the same value.
+ if (Start->getOperand(0).getReg() == ARM::LR)
+ return Start;
- auto IsMoveLR = [](MachineInstr *MI, unsigned Reg) {
+ unsigned CountReg = Start->getOperand(0).getReg();
+ auto IsMoveLR = [&CountReg](MachineInstr *MI) {
return MI->getOpcode() == ARM::tMOVr &&
MI->getOperand(0).getReg() == ARM::LR &&
- MI->getOperand(1).getReg() == Reg &&
+ MI->getOperand(1).getReg() == CountReg &&
MI->getOperand(2).getImm() == ARMCC::AL;
};
MachineBasicBlock *MBB = Start->getParent();
- unsigned CountReg = Start->getOperand(0).getReg();
- // Walk forward and backward in the block to find the closest instructions
- // that define LR. Then also filter them out if they're not a mov lr.
- MachineInstr *PredLRDef = SearchForDef(Start, MBB->rend(), ARM::LR);
- if (PredLRDef && !IsMoveLR(PredLRDef, CountReg))
- PredLRDef = nullptr;
-
- MachineInstr *SuccLRDef = SearchForDef(Start, MBB->end(), ARM::LR);
- if (SuccLRDef && !IsMoveLR(SuccLRDef, CountReg))
- SuccLRDef = nullptr;
-
- // We've either found one, two or none mov lr instructions... Now figure out
- // if they are performing the equilvant mov that the Start instruction will.
- // Do this by scanning forward and backward to see if there's a def of the
- // register holding the count value. If we find a suitable def, return it as
- // the insert point. Later, if InsertPt != Start, then we can remove the
- // redundant instruction.
- if (SuccLRDef) {
- MachineBasicBlock::iterator End(SuccLRDef);
- if (!SearchForDef(Start, End, CountReg)) {
- return SuccLRDef;
- } else
- SuccLRDef = nullptr;
- }
- if (PredLRDef) {
- MachineBasicBlock::reverse_iterator End(PredLRDef);
- if (!SearchForDef(Start, End, CountReg)) {
- return PredLRDef;
- } else
- PredLRDef = nullptr;
- }
- // We can define LR because LR already contains the same value.
- if (Start->getOperand(0).getReg() == ARM::LR)
- return Start;
+ // Find an insertion point:
+ // - Is there a (mov lr, Count) before Start? If so, and nothing else writes
+ // to Count before Start, we can insert at that mov.
+ // - Is there a (mov lr, Count) after Start? If so, and nothing else writes
+ // to Count after Start, we can insert at that mov.
+ if (auto *LRDef = RDA->getReachingMIDef(&MBB->back(), ARM::LR)) {
+ if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg))
+ return LRDef;
+ }
// We've found no suitable LR def and Start doesn't use LR directly. Can we
- // just define LR anyway?
- const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
- LivePhysRegs LiveRegs(*TRI);
- LiveRegs.addLiveOuts(*MBB);
-
- // Not if we've haven't found a suitable mov and LR is live out.
- if (LiveRegs.contains(ARM::LR))
- return nullptr;
-
- // If LR is not live out, we can insert the instruction if nothing else
- // uses LR after it.
- if (!SearchForUse(Start, MBB->end(), ARM::LR))
+ // just define LR anyway?
+ if (!RDA->isRegUsedAfter(Start, ARM::LR))
return Start;
- LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find suitable insertion point for"
- << " LR\n");
return nullptr;
}
-void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
+void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
+ ReachingDefAnalysis *RDA) {
if (Revert)
return;
@@ -320,7 +269,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
return;
}
- InsertPt = Revert ? nullptr : IsSafeToDefineLR();
+ InsertPt = Revert ? nullptr : IsSafeToDefineLR(RDA);
if (!InsertPt) {
LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n");
Revert = true;
@@ -343,6 +292,7 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "ARM Loops on " << MF->getName() << " ------------- \n");
auto &MLI = getAnalysis<MachineLoopInfo>();
+ RDA = &getAnalysis<ReachingDefAnalysis>();
MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
MRI = &MF->getRegInfo();
TII = static_cast<const ARMBaseInstrInfo*>(ST.getInstrInfo());
@@ -462,7 +412,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
if (!LoLoop.FoundAllComponents())
return false;
- LoLoop.CheckLegality(BBUtils.get());
+ LoLoop.CheckLegality(BBUtils.get(), RDA);
Expand(LoLoop);
return true;
}
@@ -493,19 +443,15 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const {
}
bool ARMLowOverheadLoops::RevertLoopDec(MachineInstr *MI,
- bool AllowFlags) const {
+ bool SetFlags) const {
LLVM_DEBUG(dbgs() << "ARM Loops: Reverting to sub: " << *MI);
MachineBasicBlock *MBB = MI->getParent();
- // If nothing uses or defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
- bool SetFlags = false;
- if (AllowFlags) {
- if (auto *Def = SearchForDef(MI, MBB->end(), ARM::CPSR)) {
- if (!SearchForUse(MI, MBB->end(), ARM::CPSR) &&
- Def->getOpcode() == ARM::t2LoopEnd)
- SetFlags = true;
- }
- }
+ // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS.
+ if (SetFlags &&
+ (RDA->isRegUsedAfter(MI, ARM::CPSR) ||
+ !RDA->hasSameReachingDef(MI, &MBB->back(), ARM::CPSR)))
+ SetFlags = false;
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
TII->get(ARM::t2SUBri));
diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll
index dd741388d749..f45302fbc1b3 100644
--- a/llvm/test/CodeGen/ARM/O3-pipeline.ll
+++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll
@@ -154,6 +154,7 @@
; CHECK-NEXT: ARM constant island placement and branch shortening pass
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: Machine Natural Loop Construction
+; CHECK-NEXT: ReachingDefAnalysis
; CHECK-NEXT: ARM Low Overhead Loops pass
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
new file mode 100644
index 000000000000..2ccb8da48d84
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir
@@ -0,0 +1,153 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
+# Check that subs isn't used during the revert because there's a def after LoopDec.
+
+--- |
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+ entry:
+ %scevgep = getelementptr i32, i32* %q, i32 -1
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1
+ call void @llvm.set.loop.iterations.i32(i32 %n)
+ %limit = lshr i32 %n, 1
+ br label %while.body
+
+ while.body: ; preds = %while.body, %entry
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
+ %tmp = phi i32 [ %n, %entry ], [ %tmp2, %while.body ]
+ %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
+ %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
+ %tmp1 = load i32, i32* %scevgep7, align 4
+ %tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1)
+ %half = lshr i32 %tmp1, 1
+ %cmp = icmp ult i32 %tmp, %limit
+ %res = select i1 %cmp, i32 %tmp1, i32 %half
+ store i32 %res, i32* %scevgep4, align 4
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+ %tmp3 = icmp ne i32 %tmp2, 0
+ br i1 %tmp3, label %while.body, label %while.end
+
+ while.end: ; preds = %while.body
+ ret i32 0
+ }
+
+ ; Function Attrs: noduplicate nounwind
+ declare void @llvm.set.loop.iterations.i32(i32) #0
+
+ ; Function Attrs: noduplicate nounwind
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+
+ ; Function Attrs: nounwind
+ declare void @llvm.stackprotector(i8*, i8**) #1
+
+ attributes #0 = { noduplicate nounwind }
+ attributes #1 = { nounwind }
+
+...
+---
+name: do_copy
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: do_copy
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: $lr = tMOVr killed $r0, 14, $noreg
+ ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+ ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+ ; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ ; CHECK: bb.1.while.body:
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
+ ; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
+ ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg
+ ; CHECK: t2IT 2, 8, implicit-def $itstate
+ ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
+ ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+ ; CHECK: t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: tBcc %bb.1, 4, killed $cpsr
+ ; CHECK: tB %bb.2, 14, $noreg
+ ; CHECK: bb.2.while.end:
+ ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ $lr = tMOVr killed $r0, 14, $noreg
+ renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+ renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg
+ t2DoLoopStart renamable $lr
+
+ bb.1.while.body:
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ liveins: $lr, $r0, $r1, $r2
+
+ renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
+ tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ t2IT 2, 8, implicit-def $itstate
+ renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+ t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr
+ tBcc %bb.1, 4, killed $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.2.while.end:
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
new file mode 100644
index 000000000000..c052e22d217d
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops -verify-machineinstrs %s -o - | FileCheck %s
+# Check that subs isn't used during the revert because there's a cpsr use after it.
+
+--- |
+ define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
+ entry:
+ %scevgep = getelementptr i32, i32* %q, i32 -1
+ %scevgep3 = getelementptr i32, i32* %p, i32 -1
+ call void @llvm.set.loop.iterations.i32(i32 %n)
+ %limit = lshr i32 %n, 1
+ br label %while.body
+
+ while.body: ; preds = %while.body, %entry
+ %lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
+ %lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
+ %tmp = phi i32 [ %n, %entry ], [ %tmp2, %while.body ]
+ %scevgep7 = getelementptr i32, i32* %lsr.iv, i32 1
+ %scevgep4 = getelementptr i32, i32* %lsr.iv4, i32 1
+ %tmp1 = load i32, i32* %scevgep7, align 4
+ %tmp2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp, i32 1)
+ %half = lshr i32 %tmp1, 1
+ %cmp = icmp ult i32 %tmp, %limit
+ %res = select i1 %cmp, i32 %tmp1, i32 %half
+ store i32 %res, i32* %scevgep4, align 4
+ %scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
+ %scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
+ %tmp3 = icmp ne i32 %tmp2, 0
+ br i1 %tmp3, label %while.body, label %while.end
+
+ while.end: ; preds = %while.body
+ ret i32 0
+ }
+
+ ; Function Attrs: noduplicate nounwind
+ declare void @llvm.set.loop.iterations.i32(i32) #0
+
+ ; Function Attrs: noduplicate nounwind
+ declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
+
+ ; Function Attrs: nounwind
+ declare void @llvm.stackprotector(i8*, i8**) #1
+
+ attributes #0 = { noduplicate nounwind }
+ attributes #1 = { nounwind }
+
+...
+---
+name: do_copy
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: do_copy
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+ ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+ ; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
+ ; CHECK: $lr = tMOVr killed $r0, 14, $noreg
+ ; CHECK: bb.1.while.body:
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $r0, $r1, $r2
+ ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
+ ; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
+ ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg
+ ; CHECK: t2IT 2, 8, implicit-def $itstate
+ ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
+ ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+ ; CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: tBcc %bb.1, 1, $cpsr
+ ; CHECK: tB %bb.2, 14, $noreg
+ ; CHECK: bb.2.while.end:
+ ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+ bb.0.entry:
+ successors: %bb.1(0x80000000)
+ liveins: $r0, $r1, $r2, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
+ renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
+ t2DoLoopStart renamable $r0
+ renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg
+ $lr = tMOVr killed $r0, 14, $noreg
+
+ bb.1.while.body:
+ successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ liveins: $lr, $r0, $r1, $r2
+
+ renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
+ tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ t2IT 2, 8, implicit-def $itstate
+ renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate
+ early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4)
+ t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
+ tB %bb.2, 14, $noreg
+
+ bb.2.while.end:
+ $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+ tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
+
+...
diff --git a/llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir b/llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
index 58ddfcc2a683..1f5edb0c78b9 100644
--- a/llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
+++ b/llvm/test/CodeGen/Thumb2/ifcvt-neon-deprecated.mir
@@ -1,54 +1,89 @@
-# RUN: llc -mtriple=thumbv7 -start-before=if-converter -o - %s | FileCheck %s
+# RUN: llc -mtriple=thumbv7 -start-before=if-converter %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'vdup-test.ll'
+ source_filename = "vdup-test.ll"
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv7"
+
+ define arm_aapcs_vfpcc <2 x i32> @NeonVdupMul(i32 %scalar, i32 %N, <2 x i32> %vector) {
+ entry:
+ %cmp = icmp ne i32 %N, 0
+ %broadcast = insertelement <2 x i32> undef, i32 %scalar, i32 0
+ %dup = shufflevector <2 x i32> %broadcast, <2 x i32> undef, <2 x i32> zeroinitializer
+ %mul = mul <2 x i32> %dup, %vector
+ br i1 %cmp, label %select.end, label %select.false
+
+ select.false: ; preds = %entry
+ br label %select.end
+
+ select.end: ; preds = %entry, %select.false
+ %res = phi <2 x i32> [ %mul, %entry ], [ %vector, %select.false ]
+ ret <2 x i32> %res
+ }
+
+...
---
name: NeonVdupMul
+alignment: 2
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$d0', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 1
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack: []
+callSites: []
+constants: []
+machineFunctionInfo: {}
body: |
- bb.0:
- successors: %bb.2, %bb.1
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $d0, $r0, $r1
-
- t2CMPri killed $r1, 0, 14, $noreg, implicit-def $cpsr
+
+ t2CMPri killed renamable $r1, 0, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.2, 0, killed $cpsr
-
+
bb.1:
+ successors: %bb.2(0x80000000)
liveins: $d0, $r0
-
- $d16 = VDUP32d killed $r0, 14, $noreg
+
+ renamable $d16 = VDUP32d killed renamable $r0, 14, $noreg
; Verify that the neon instructions haven't been conditionalized:
; CHECK-LABEL: NeonVdupMul
; CHECK: vdup.32
; CHECK: vmul.i32
- $d0 = VMULv2i32 killed $d16, killed $d0, 14, $noreg
-
- bb.2:
+ renamable $d0 = VMULv2i32 killed renamable $d16, killed renamable $d0, 14, $noreg
+
+ bb.2.select.end:
liveins: $d0
-
- tBX_RET 14, $noreg, implicit $d0
-
-...
----
-name: NeonVmovVfpLdr
-body: |
- bb.0.entry:
- successors: %bb.1, %bb.2
- liveins: $r0, $r1
-
- t2CMPri killed $r1, 0, 14, $noreg, implicit-def $cpsr
- t2Bcc %bb.2, 1, killed $cpsr
-
- bb.1:
- $d0 = VMOVv2i32 0, 14, $noreg
- tBX_RET 14, $noreg, implicit $d0
-
- bb.2:
- liveins: $r0
-
- $d0 = VLDRD killed $r0, 0, 14, $noreg
- ; Verify that the neon instruction VMOVv2i32 hasn't been conditionalized,
- ; but the VLDR instruction that is available both in the VFP and Advanced
- ; SIMD extensions has.
- ; CHECK-LABEL: NeonVmovVfpLdr
- ; CHECK-DAG: vmov.i32 d0, #0x0
- ; CHECK-DAG: vldr{{ne|eq}} d0, [r0]
+
tBX_RET 14, $noreg, implicit $d0
...
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