[llvm] 4a59eed - [ARM][ConstantIslands] Correct block size update
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 26 01:56:55 PST 2019
Author: Sam Parker
Date: 2019-11-26T09:55:58Z
New Revision: 4a59eedd2d1d942a30f6ba016168c6430f9c165c
URL: https://github.com/llvm/llvm-project/commit/4a59eedd2d1d942a30f6ba016168c6430f9c165c
DIFF: https://github.com/llvm/llvm-project/commit/4a59eedd2d1d942a30f6ba016168c6430f9c165c.diff
LOG: [ARM][ConstantIslands] Correct block size update
When inserting a non-decrementing LE, the basic block was being
resized to take into consideration that a tCMP and tBcc had been
combined into one T1 instruction. This is not true in the LE case
where we generate a CBN?Z and an LE.
Differential Revision: https://reviews.llvm.org/D70536
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
Modified:
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 24ca25f73e96..634fb89b8e89 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1917,6 +1917,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() {
MachineInstrBuilder MIB = BuildMI(*MBB, Br.MI, Br.MI->getDebugLoc(),
TII->get(ARM::t2LE));
+ // Swapped a t2Bcc for a t2LE, so no need to update the size of the block.
MIB.add(Br.MI->getOperand(0));
Br.MI->eraseFromParent();
Br.MI = MIB;
@@ -1975,21 +1976,20 @@ bool ARMConstantIslands::optimizeThumb2Branches() {
.addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
Cmp.MI->eraseFromParent();
- BBInfoVector &BBInfo = BBUtils->getBBInfo();
- BBInfo[MBB->getNumber()].Size -= 2;
if (Br.MI->getOpcode() == ARM::tBcc) {
Br.MI->eraseFromParent();
Br.MI = NewBR;
- } else if (&MBB->back() != Br.MI) {
- // We've generated an LE and already erased the original conditional
- // branch. The CBN?Z is now used to branch to the other successor, so an
- // unconditional branch terminator is now redundant.
+ BBUtils->adjustBBSize(MBB, -2);
+ } else if (MBB->back().getOpcode() != ARM::t2LE) {
+ // An LE has been generated, but it's not the terminator - that is an
+ // unconditional branch. However, the logic has now been reversed with the
+ // CBN?Z being the conditional branch and the LE being the unconditional
+ // branch. So this means we can remove the redundant unconditional branch
+ // at the end of the block.
MachineInstr *LastMI = &MBB->back();
- if (LastMI != Br.MI) {
- BBInfo[MBB->getNumber()].Size -= LastMI->getDesc().getSize();
- LastMI->eraseFromParent();
- }
+ BBUtils->adjustBBSize(MBB, -LastMI->getDesc().getSize());
+ LastMI->eraseFromParent();
}
BBUtils->adjustBBOffsetsAfter(MBB);
++NumCBZ;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
new file mode 100644
index 000000000000..c5a38ea13454
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir
@@ -0,0 +1,451 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-cp-islands %s -o - | FileCheck %s
+--- |
+ @d = hidden local_unnamed_addr global i32 0, align 4
+ @a = hidden global i32 0, align 4
+ @e = hidden local_unnamed_addr global i32 0, align 4
+
+ define hidden void @f(i64 %g) {
+ entry:
+ %conv = trunc i64 %g to i32
+ %tobool5 = icmp eq i64 %g, 0
+ br i1 %tobool5, label %j.us.us.preheader, label %entry.split
+
+ j.us.us.preheader: ; preds = %entry
+ %.pre59 = load i32, i32* @d, align 4
+ br label %j.us.us
+
+ j.us.us: ; preds = %j.us.us, %if.end.us.us.us, %if.end.us.us.us.1, %if.end.us.us.us.2, %if.end.us.us.us.3, %if.end.us.us.us.4, %if.end.us.us.us.5, %if.end.us.us.us.6, %j.us.us.preheader
+ %0 = phi i32 [ %.pre59, %j.us.us.preheader ], [ %12, %if.end.us.us.us.6 ], [ %11, %if.end.us.us.us.5 ], [ %10, %if.end.us.us.us.4 ], [ %9, %if.end.us.us.us.3 ], [ %8, %if.end.us.us.us.2 ], [ %7, %if.end.us.us.us.1 ], [ %2, %if.end.us.us.us ], [ %0, %j.us.us ]
+ %cmp.us.us = icmp slt i32 %0, ptrtoint (i32* @a to i32)
+ %conv1.us.us = zext i1 %cmp.us.us to i32
+ %1 = load i32, i32* @e, align 4
+ %and.us.us = and i32 %1, %conv1.us.us
+ store i32 %and.us.us, i32* @e, align 4
+ %tobool4.us.us.us = icmp eq i32 %0, 0
+ br i1 %tobool4.us.us.us, label %if.end.us.us.us, label %j.us.us
+
+ if.end.us.us.us: ; preds = %j.us.us
+ tail call void asm sideeffect "", ""()
+ %2 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.1 = icmp eq i32 %2, 0
+ br i1 %tobool4.us.us.us.1, label %if.end.us.us.us.1, label %j.us.us
+
+ entry.split: ; preds = %entry
+ %tobool = icmp eq i32 %conv, 0
+ br i1 %tobool, label %j.us27.preheader, label %j.preheader
+
+ j.preheader: ; preds = %entry.split
+ %.pre = load i32, i32* @e, align 4
+ %.pre55 = load i32, i32* @d, align 4
+ %cmp = icmp slt i32 %conv, ptrtoint (i32* @a to i32)
+ %conv1 = zext i1 %cmp to i32
+ br label %j
+
+ j.us27.preheader: ; preds = %entry.split
+ %.pre56 = load i32, i32* @d, align 4
+ %.pre57 = load i32, i32* @e, align 4
+ %cmp.us29 = icmp slt i32 %.pre56, ptrtoint (i32* @a to i32)
+ %conv1.us30 = zext i1 %cmp.us29 to i32
+ br label %j.us27
+
+ j.us27: ; preds = %j.us27, %j.us27.preheader
+ %3 = phi i32 [ %.pre57, %j.us27.preheader ], [ %and.us31, %j.us27 ]
+ %4 = icmp eq i32 %.pre56, 0
+ %and.us31 = and i32 %3, %conv1.us30
+ br i1 %4, label %if.end.us38, label %j.us27
+
+ if.end.us38: ; preds = %j.us27
+ store i32 %and.us31, i32* @e, align 4
+ tail call void asm sideeffect "", ""()
+ ret void
+
+ j: ; preds = %j, %j.preheader
+ %5 = phi i32 [ %.pre, %j.preheader ], [ %and, %j ]
+ %6 = icmp eq i32 %.pre55, 0
+ %and = and i32 %5, %conv1
+ br i1 %6, label %if.end, label %j
+
+ if.end: ; preds = %j
+ store i32 %and, i32* @e, align 4
+ tail call void asm sideeffect "", ""()
+ ret void
+
+ if.end.us.us.us.1: ; preds = %if.end.us.us.us
+ tail call void asm sideeffect "", ""()
+ %7 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.2 = icmp eq i32 %7, 0
+ br i1 %tobool4.us.us.us.2, label %if.end.us.us.us.2, label %j.us.us
+
+ if.end.us.us.us.2: ; preds = %if.end.us.us.us.1
+ tail call void asm sideeffect "", ""()
+ %8 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.3 = icmp eq i32 %8, 0
+ br i1 %tobool4.us.us.us.3, label %if.end.us.us.us.3, label %j.us.us
+
+ if.end.us.us.us.3: ; preds = %if.end.us.us.us.2
+ tail call void asm sideeffect "", ""()
+ %9 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.4 = icmp eq i32 %9, 0
+ br i1 %tobool4.us.us.us.4, label %if.end.us.us.us.4, label %j.us.us
+
+ if.end.us.us.us.4: ; preds = %if.end.us.us.us.3
+ tail call void asm sideeffect "", ""()
+ %10 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.5 = icmp eq i32 %10, 0
+ br i1 %tobool4.us.us.us.5, label %if.end.us.us.us.5, label %j.us.us
+
+ if.end.us.us.us.5: ; preds = %if.end.us.us.us.4
+ tail call void asm sideeffect "", ""()
+ %11 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.6 = icmp eq i32 %11, 0
+ br i1 %tobool4.us.us.us.6, label %if.end.us.us.us.6, label %j.us.us
+
+ if.end.us.us.us.6: ; preds = %if.end.us.us.us.5
+ tail call void asm sideeffect "", ""()
+ %12 = load i32, i32* @d, align 4
+ %tobool4.us.us.us.7 = icmp eq i32 %12, 0
+ br i1 %tobool4.us.us.us.7, label %if.end.us.us.us.7, label %j.us.us
+
+ if.end.us.us.us.7: ; preds = %if.end.us.us.us.6
+ tail call void asm sideeffect "", ""()
+ ret void
+ }
+
+...
+---
+name: f
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 8
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+constants: []
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: f
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.5(0x30000000), %bb.1(0x50000000)
+ ; CHECK: liveins: $r0, $r1, $r7, $lr
+ ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
+ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
+ ; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14, $noreg
+ ; CHECK: tBcc %bb.5, 0, killed $cpsr
+ ; CHECK: bb.1.entry.split:
+ ; CHECK: successors: %bb.15(0x30000000), %bb.2(0x50000000)
+ ; CHECK: liveins: $r0
+ ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+ ; CHECK: tBcc %bb.15, 0, killed $cpsr
+ ; CHECK: bb.2.j.preheader:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: liveins: $r0
+ ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg
+ ; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr
+ ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14, $noreg
+ ; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg
+ ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+ ; CHECK: bb.3.j (align 4):
+ ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+ ; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14, $noreg
+ ; CHECK: tCBZ $r2, %bb.4
+ ; CHECK: bb.4.if.end:
+ ; CHECK: liveins: $r1, $r3
+ ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e)
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ ; CHECK: bb.5.j.us.us.preheader:
+ ; CHECK: successors: %bb.6(0x80000000)
+ ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ ; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14, $noreg
+ ; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14, $noreg
+ ; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14, $noreg
+ ; CHECK: bb.6.j.us.us (align 4):
+ ; CHECK: successors: %bb.7(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r3, $r12
+ ; CHECK: tCMPhir renamable $r3, renamable $lr, 14, $noreg, implicit-def $cpsr
+ ; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+ ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ ; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14, $noreg, $noreg
+ ; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14, $noreg :: (store 4 into @e)
+ ; CHECK: tCBZ $r3, %bb.7
+ ; CHECK: bb.7.if.end.us.us.us:
+ ; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.8
+ ; CHECK: bb.8.if.end.us.us.us.1:
+ ; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.9
+ ; CHECK: bb.9.if.end.us.us.us.2:
+ ; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.10
+ ; CHECK: bb.10.if.end.us.us.us.3:
+ ; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.11
+ ; CHECK: bb.11.if.end.us.us.us.4:
+ ; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.12
+ ; CHECK: bb.12.if.end.us.us.us.5:
+ ; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.13
+ ; CHECK: bb.13.if.end.us.us.us.6:
+ ; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000)
+ ; CHECK: liveins: $lr, $r2, $r12
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCBZ $r3, %bb.14
+ ; CHECK: bb.14.if.end.us.us.us.7:
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ ; CHECK: bb.15.j.us27.preheader:
+ ; CHECK: successors: %bb.16(0x80000000)
+ ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ ; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14, $noreg
+ ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg
+ ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ ; CHECK: tCMPr renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr
+ ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg
+ ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+ ; CHECK: bb.16.j.us27 (align 4):
+ ; CHECK: successors: %bb.17(0x04000000), %bb.16(0x7c000000)
+ ; CHECK: liveins: $r0, $r1, $r2, $r3
+ ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14, $noreg
+ ; CHECK: tCBZ $r0, %bb.17
+ ; CHECK: bb.17.if.end.us38:
+ ; CHECK: liveins: $r1, $r3
+ ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e)
+ ; CHECK: INLINEASM &"", 1
+ ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
+ bb.0.entry:
+ successors: %bb.1(0x30000000), %bb.11(0x50000000)
+ liveins: $r0, $r1, $r7, $lr
+
+ frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 8
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14, $noreg
+ t2Bcc %bb.1, 0, killed $cpsr
+
+ bb.11.entry.split:
+ successors: %bb.15(0x30000000), %bb.12(0x50000000)
+ liveins: $r0
+
+ tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.15, 0, killed $cpsr
+
+ bb.12.j.preheader:
+ successors: %bb.13(0x80000000)
+ liveins: $r0
+
+ $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg
+ tCMPr killed renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr
+ $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14, $noreg
+ renamable $r2 = tLDRi killed renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg
+ renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+
+ bb.13.j (align 4):
+ successors: %bb.14(0x04000000), %bb.13(0x7c000000)
+ liveins: $r0, $r1, $r2, $r3
+
+ renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14, $noreg
+ tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.13, 1, killed $cpsr
+
+ bb.14.if.end:
+ liveins: $r1, $r3
+
+ tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e)
+ INLINEASM &"", 1
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+ bb.1.j.us.us.preheader:
+ successors: %bb.2(0x80000000)
+
+ $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ $lr = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14, $noreg
+ $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14, $noreg
+ $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14, $noreg
+
+ bb.2.j.us.us (align 4):
+ successors: %bb.3(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r3, $r12
+
+ tCMPhir renamable $r3, renamable $lr, 14, $noreg, implicit-def $cpsr
+ renamable $r1 = tLDRi renamable $r2, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+ renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14, $noreg, $noreg
+ tSTRi killed renamable $r0, renamable $r2, 0, 14, $noreg :: (store 4 into @e)
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.3.if.end.us.us.us:
+ successors: %bb.4(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.4.if.end.us.us.us.1:
+ successors: %bb.5(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.5.if.end.us.us.us.2:
+ successors: %bb.6(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.6.if.end.us.us.us.3:
+ successors: %bb.7(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.7.if.end.us.us.us.4:
+ successors: %bb.8(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.8.if.end.us.us.us.5:
+ successors: %bb.9(0x40000000), %bb.2(0x40000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.9.if.end.us.us.us.6:
+ successors: %bb.10(0x04000000), %bb.2(0x7c000000)
+ liveins: $lr, $r2, $r12
+
+ INLINEASM &"", 1
+ renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.2, 1, killed $cpsr
+
+ bb.10.if.end.us.us.us.7:
+ INLINEASM &"", 1
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+ bb.15.j.us27.preheader:
+ successors: %bb.16(0x80000000)
+
+ $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg
+ $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg
+ $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg
+ renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (dereferenceable load 4 from @d)
+ tCMPr renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr
+ $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg
+ renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr
+ renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e)
+
+ bb.16.j.us27 (align 4):
+ successors: %bb.17(0x04000000), %bb.16(0x7c000000)
+ liveins: $r0, $r1, $r2, $r3
+
+ renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14, $noreg
+ tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr
+ t2Bcc %bb.16, 1, killed $cpsr
+
+ bb.17.if.end.us38:
+ liveins: $r1, $r3
+
+ tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e)
+ INLINEASM &"", 1
+ tPOP_RET 14, $noreg, def $r7, def $pc
+
+...
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