[PATCH] D70650: [MC] Rewrite tablegen for printInstrAlias to comiple faster, NFC
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 25 11:41:33 PST 2019
craig.topper added inline comments.
================
Comment at: llvm/utils/TableGen/AsmWriterEmitter.cpp:678
- void print(raw_ostream &O) {
- if (Conds.empty()) {
- O.indent(6) << "return true;\n";
- return;
- }
-
- O << "if (";
-
- for (std::vector<std::string>::iterator
- I = Conds.begin(), E = Conds.end(); I != E; ++I) {
- if (I != Conds.begin()) {
- O << " &&\n";
- O.indent(8);
- }
-
- O << *I;
- }
-
- O << ") {\n";
- O.indent(6) << "// " << Result << "\n";
-
+ std::string print(uint32_t &UnescapedSize) {
// Directly mangle mapped operands into the string. Each operand is
----------------
Should we rename this since it doesn't print to a stream anymore?
================
Comment at: llvm/utils/TableGen/AsmWriterEmitter.cpp:819
NumMIOps += ResultInstOpnd.MINumOperands;
-
- std::string Cond;
- Cond = std::string("MI->getNumOperands() == ") + utostr(NumMIOps);
- IAP.addCond(Cond);
+ IAP.setNumMIOps(NumMIOps);
----------------
Can we move the IAP object down and pass this to the constructor?
================
Comment at: llvm/utils/TableGen/AsmWriterEmitter.cpp:922
- Cond = Op + ".getReg() == " + Target.getName().str() + "::" +
- CGA.ResultOperands[i].getRegister()->getName().str();
- IAP.addCond(Cond);
+ StringRef Reg = CGA.ResultOperands[i].getRegister()->getName();
+ IAP.addCond(
----------------
Bad identation here
================
Comment at: llvm/utils/TableGen/AsmWriterEmitter.cpp:955
+ bool IsNeg = Op[0] == '!';
+ StringRef Feature = StringRef(Op).drop_front(IsNeg ? 1 : 0);
+ IAP.addCond(formatv("AliasPatternCond::K_{0}Feature, {1}::{2}",
----------------
Why StringRef(Op)? Isn't Op already a StringRef?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D70650/new/
https://reviews.llvm.org/D70650
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