[PATCH] D70407: [ARM] Generate CMSE instructions from CMSE intrinsics
Momchil Velikov via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 25 10:36:16 PST 2019
This revision was automatically updated to reflect the committed changes.
Closed by commit rG09555ce07176: [ARM] Generate CMSE instructions from CMSE intrinsics (authored by chill).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D70407/new/
https://reviews.llvm.org/D70407
Files:
llvm/lib/Target/ARM/ARMInstrThumb2.td
llvm/test/CodeGen/ARM/intrinsics-cmse.ll
Index: llvm/test/CodeGen/ARM/intrinsics-cmse.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/intrinsics-cmse.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mtriple=thumbv8m.base | FileCheck %s
+; RUN: llc < %s -mtriple=thumbebv8m.base | FileCheck %s
+
+define i32 @test_tt(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.tt(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_tt:
+; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.tt(i8*) #1
+
+define i32 @test_ttt(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.ttt(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_ttt:
+; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.ttt(i8*) #1
+
+define i32 @test_tta(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.tta(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_tta:
+; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.tta(i8*) #1
+
+define i32 @test_ttat(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.ttat(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_ttat:
+; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.ttat(i8*) #1
+
+attributes #0 = { nounwind readnone "target-features"="+8msecext"}
+attributes #1 = { nounwind readnone }
Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -4551,10 +4551,18 @@
let Unpredictable{5-0} = 0b111111;
}
-def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TT : T2TT<0b00, "tt",
+ [(set rGPR:$Rt, (int_arm_cmse_tt GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTT : T2TT<0b01, "ttt",
+ [(set rGPR:$Rt, (int_arm_cmse_ttt GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTA : T2TT<0b10, "tta",
+ [(set rGPR:$Rt, (int_arm_cmse_tta GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTAT : T2TT<0b11, "ttat",
+ [(set rGPR:$Rt, (int_arm_cmse_ttat GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
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