[llvm] 09555ce - [ARM] Generate CMSE instructions from CMSE intrinsics
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 25 10:27:18 PST 2019
Author: Momchil Velikov
Date: 2019-11-25T18:26:12Z
New Revision: 09555ce07176d279e8ba8bdb74bb8dbff0a3cb82
URL: https://github.com/llvm/llvm-project/commit/09555ce07176d279e8ba8bdb74bb8dbff0a3cb82
DIFF: https://github.com/llvm/llvm-project/commit/09555ce07176d279e8ba8bdb74bb8dbff0a3cb82.diff
LOG: [ARM] Generate CMSE instructions from CMSE intrinsics
This patch adds instruction selection patterns for the TT, TTT, TTA, and TTAT
instructions and tests for llvm.arm.cmse.tt, llvm.arm.cmse.ttt,
llvm.arm.cmse.tta, and llvm.arm.cmse.ttat intrinsics (added in a previous
patch).
Patch by Javed Absar.
Differential Revision: https://reviews.llvm.org/D70407
Added:
llvm/test/CodeGen/ARM/intrinsics-cmse.ll
Modified:
llvm/lib/Target/ARM/ARMInstrThumb2.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 25a45b39fa0c..7044c92a7f11 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -4551,10 +4551,18 @@ class T2TT<bits<2> at, string asm, list<dag> pattern>
let Unpredictable{5-0} = 0b111111;
}
-def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>;
-def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>;
+def t2TT : T2TT<0b00, "tt",
+ [(set rGPR:$Rt, (int_arm_cmse_tt GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTT : T2TT<0b01, "ttt",
+ [(set rGPR:$Rt, (int_arm_cmse_ttt GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTA : T2TT<0b10, "tta",
+ [(set rGPR:$Rt, (int_arm_cmse_tta GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
+def t2TTAT : T2TT<0b11, "ttat",
+ [(set rGPR:$Rt, (int_arm_cmse_ttat GPRnopc:$Rn))]>,
+ Requires<[IsThumb, Has8MSecExt]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
diff --git a/llvm/test/CodeGen/ARM/intrinsics-cmse.ll b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll
new file mode 100644
index 000000000000..be4fed19665a
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/intrinsics-cmse.ll
@@ -0,0 +1,45 @@
+; RUN: llc < %s -mtriple=thumbv8m.base | FileCheck %s
+; RUN: llc < %s -mtriple=thumbebv8m.base | FileCheck %s
+
+define i32 @test_tt(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.tt(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_tt:
+; CHECK: tt r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.tt(i8*) #1
+
+define i32 @test_ttt(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.ttt(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_ttt:
+; CHECK: ttt r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.ttt(i8*) #1
+
+define i32 @test_tta(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.tta(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_tta:
+; CHECK: tta r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.tta(i8*) #1
+
+define i32 @test_ttat(i8* readnone %p) #0 {
+entry:
+ %0 = tail call i32 @llvm.arm.cmse.ttat(i8* %p)
+ ret i32 %0
+}
+; CHECK-LABEL: test_ttat:
+; CHECK: ttat r{{[0-9]+}}, r{{[0-9]+}}
+
+declare i32 @llvm.arm.cmse.ttat(i8*) #1
+
+attributes #0 = { nounwind readnone "target-features"="+8msecext"}
+attributes #1 = { nounwind readnone }
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