[PATCH] D29014: [SelDag][MIR] Add FREEZE

[Juneyoung Lee via Phabricator via llvm-commits]

aqjune updated this revision to Diff 230899.
aqjune edited the summary of this revision.
aqjune added a comment.

I added description about FREEZE and IMPLICIT_DEF to `TargetOpcodes.def`.
To address the legalization issue, updated the semantics so FREEZEs return the same value if placed consecutively. Would this properly address the issue?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D29014/new/

https://reviews.llvm.org/D29014

Files:
  llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
  llvm/include/llvm/CodeGen/AsmPrinter.h
  llvm/include/llvm/CodeGen/FastISel.h
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/CodeGen/SelectionDAGISel.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp
  llvm/lib/CodeGen/TargetPassConfig.cpp
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/test/CodeGen/X86/fast-isel-freeze.ll
  llvm/test/CodeGen/X86/fast-isel.ll
  llvm/test/CodeGen/X86/freeze-call.ll
  llvm/test/CodeGen/X86/freeze-legalize.ll
  llvm/test/CodeGen/X86/freeze-mir.ll
  llvm/test/CodeGen/X86/freeze-phielim.ll
  llvm/test/CodeGen/X86/freeze.ll

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