[PATCH] D62190: [RISCV] Allow shrink wrapping for RISC-V

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

In D62190#1755258 <https://reviews.llvm.org/D62190#1755258>, @lewis-revill wrote:

> In D62190#1755159 <https://reviews.llvm.org/D62190#1755159>, @asb wrote:
>
> > I note that the TargetFrameLowering hooks `canUseAsPrologue` and `canUseAsEpilogue` are both called by the shrink wrapper. They default to true, but targets may need to override this for correctness. Looking at e.g. AArch64, I see it overrides `canUseAsPrologue` and returns false in the case that the function needs stack realignment and there are no scratch registers available. Are you certain that no such case is needed for RISC-V?
>
>
> So I see that the stack realignment implementation for larger values does indeed require the use of a scratch register, so that implies we should attempt to prevent the situation where we don't have one available. However the scratch register is created as a virtual GPR register, rather than attempting to scavenge a real free register. I can imagine that if this was changed, we could directly perform the same check in `canUseAsPrologue` to guarantee a register being available in a much more transparent and obvious way. EG the way in which AArch64 uses the function `findScratchNonCalleeSaveRegister`.


I'm working on a patch for the realignment implementation based off issues that arose with implementing the ilp32e ABI. I will update this thread when that patch is ready.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62190/new/

https://reviews.llvm.org/D62190