[llvm] b8e6319 - [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp

[David Tellenbach via llvm-commits]

Author: David Tellenbach
Date: 2019-11-23T19:11:31+01:00
New Revision: b8e6319f3ef7f9e87cecefc73326dd025455c019

URL: https://github.com/llvm/llvm-project/commit/b8e6319f3ef7f9e87cecefc73326dd025455c019
DIFF: https://github.com/llvm/llvm-project/commit/b8e6319f3ef7f9e87cecefc73326dd025455c019.diff

LOG: [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedPredicates.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
index 028ad2232c9b..fc13b23b4cf8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td
@@ -322,7 +322,7 @@ def IsLoadRegOffsetOp      : CheckOpcode<[PRFMroW, PRFMroX,
                                           LDRDroW, LDRDroX,
                                           LDRQroW, LDRQroX]>;
 
-// Identify whether an instruction is a load
+// Identify whether an instruction is a store
 // using the register offset addressing mode.
 def IsStoreRegOffsetOp     : CheckOpcode<[STRBBroW, STRBBroX,
                                           STRHHroW, STRHHroX,