[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[qshanz via Phabricator via llvm-commits]

steven.zhang added inline comments.


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp:1540
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+
----------------
kparzysz wrote:
> The types should be `v2i8`, `v4i8`, and `v2i16`.
I just only see two match pattern for this ISD Node in the TD file, and no match pattern for v4i8. Did I miss something ?
```
def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i8)),
         (Combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>;

def: Pat<(v2i32 (sext_inreg V2I32:$Rs, v2i16)),
         (Combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>;
```


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp:203
+    setOperationAction(ISD::SIGN_EXTEND_INREG, T,  Legal);
+
   setTargetDAGCombine(ISD::VSELECT);
----------------
kparzysz wrote:
> Please replace this with
> 
> ```
> if (Use64b) {
>   for (MVT T : {MVT::v16i8, MVT::v32i8, MVT::v16i16})
>     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
> } else {
>   for (MVT T : {MVT::v32i8, MVT::v64i8, MVT::v32i16})
>     setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
> }
> ```
We need to mark the dest type as Legal too, as Vector Op Legalizer will check the operand 0 instead of the Operand 1 is legal or not. That is important for some target to support:
```
  v4i32 sext_inreg Val, v4i8
  v4i16 sext_inreg Val, v4i8
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000