[PATCH] D70000: [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added inline comments.


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp:1540
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
+
----------------
The types should be `v2i8`, `v4i8`, and `v2i16`.


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp:23
+static const MVT InRegV128[] = { MVT::v64i8, MVT::v64i16, MVT::v32i8,
+                                 MVT::v32i16, MVT::v32i32 };
 
----------------
Please do not use globals for this.


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp:64
   ArrayRef<MVT> LegalW = Use64b ? LegalW64 : LegalW128;
+  ArrayRef<MVT> InRegV = Use64b ? InRegV64 : InRegV128;
   MVT ByteV = Use64b ?  MVT::v64i8 : MVT::v128i8;
----------------
Please remove this.


================
Comment at: llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp:203
+    setOperationAction(ISD::SIGN_EXTEND_INREG, T,  Legal);
+
   setTargetDAGCombine(ISD::VSELECT);
----------------
Please replace this with

```
if (Use64b) {
  for (MVT T : {MVT::v16i8, MVT::v32i8, MVT::v16i16})
    setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
} else {
  for (MVT T : {MVT::v32i8, MVT::v64i8, MVT::v32i16})
    setOperationAction(ISD::SIGN_EXTEND_INREG, T, Legal);
}
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70000/new/

https://reviews.llvm.org/D70000