[PATCH] D70614: AMDGPU: Reuse carry out register during FI elimination

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1133
+              Register ConstOffsetReg;
+              if (RC == &AMDGPU::SReg_64RegClass)
+                ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0);
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It would be slightly safer to directly check wave32 or not than relying on getting the physreg class and directly checking it. Sometimes the exact subclass changes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70614/new/

https://reviews.llvm.org/D70614