[PATCH] D70490: [mips] Add a 'generic' Mips CPU

[Miloš Stojanović via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6ba5cbf3ea23: [mips] Add a 'generic' Mips CPU (authored by mstojanovic).
Herald added a subscriber: jrtc27.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70490/new/

https://reviews.llvm.org/D70490

Files:
  llvm/lib/Target/Mips/Mips.td
  llvm/test/CodeGen/Mips/cpus.ll


Index: llvm/test/CodeGen/Mips/cpus.ll
===================================================================
--- llvm/test/CodeGen/Mips/cpus.ll
+++ llvm/test/CodeGen/Mips/cpus.ll
@@ -1,5 +1,9 @@
 ; Check that the CPU names work.
 
+; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \
+; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=GENERIC
+; GENERIC: ISA: MIPS32
+
 ; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \
 ; RUN:   | llvm-readelf -A | FileCheck %s --check-prefix=MIPS2
 ; MIPS2: ISA: MIPS2
Index: llvm/lib/Target/Mips/Mips.td
===================================================================
--- llvm/lib/Target/Mips/Mips.td
+++ llvm/lib/Target/Mips/Mips.td
@@ -232,6 +232,7 @@
 class Proc<string Name, list<SubtargetFeature> Features>
  : ProcessorModel<Name, MipsGenericModel, Features>;
 
+def : Proc<"generic", [FeatureMips32]>;
 def : Proc<"mips1", [FeatureMips1]>;
 def : Proc<"mips2", [FeatureMips2]>;
 def : Proc<"mips32", [FeatureMips32]>;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D70490.230449.patch
Type: text/x-patch
Size: 986 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20191121/a22abf73/attachment.bin>