[PATCH] D70176: [Codegen][ARM] Add addressing modes from masked loads and stores

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

It would be good to see this rebased since the tail predication changes went in.



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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:387
+      setIndexedMaskedLoadAction(im, VT, Legal);
+      setIndexedMaskedStoreAction(im, VT, Legal);
+    }
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Why not v4i32 and floats too?


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:15566
 
+  bool CanChangeType = isLE && !IsMasked;
+
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Maybe add a comment here for why we have this restriction?


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Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:5312
+                                          PatFrag StoreKind, int shift>
+  : Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr, VCCR:$pred),
+        (Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr, (i32 1), VCCR:$pred)>;
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I don't think we shouldn't be restricting the base to a T1 register.


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  https://reviews.llvm.org/D70176/new/

https://reviews.llvm.org/D70176