[llvm] cc80695 - [mips] Remove unused `IsPCRelativeLoad` MIPS instructions attribute. NFC

[Simon Atanasyan via llvm-commits]

Author: Simon Atanasyan
Date: 2019-11-21T13:50:14+03:00
New Revision: cc80695f6f17f922ce91f18804b44af89ed21f27

URL: https://github.com/llvm/llvm-project/commit/cc80695f6f17f922ce91f18804b44af89ed21f27
DIFF: https://github.com/llvm/llvm-project/commit/cc80695f6f17f922ce91f18804b44af89ed21f27.diff

LOG: [mips] Remove unused `IsPCRelativeLoad` MIPS instructions attribute. NFC

This attribute is always set to zero.

Added: 
    

Modified: 
    llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
    llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
    llvm/lib/Target/Mips/MipsInstrFormats.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 69c978d0b637..7f5281217953 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -2129,8 +2129,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
     ExpandedJalSym = true;
   }
 
-  bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0;
-  if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) {
+  if (MCID.mayLoad() || MCID.mayStore()) {
     // Check the offset of memory operand, if it is a symbol
     // reference or immediate we may have to expand instructions.
     if (needsExpandMemInst(Inst)) {

diff  --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
index 6d8cb264158f..3c11edfc3fc7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
@@ -123,11 +123,8 @@ namespace MipsII {
     IsCTI = 1 << 4,
     /// HasForbiddenSlot - Instruction has a forbidden slot.
     HasForbiddenSlot = 1 << 5,
-    /// IsPCRelativeLoad - A Load instruction with implicit source register
-    ///                    ($pc) with explicit offset and destination register
-    IsPCRelativeLoad = 1 << 6,
     /// HasFCCRegOperand - Instruction uses an $fcc<x> register.
-    HasFCCRegOperand = 1 << 7
+    HasFCCRegOperand = 1 << 6
 
   };
 }

diff  --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index af7cdbe5d609..4624c1f2d04a 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -97,9 +97,6 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
   bit isCTI            = 0; // Any form of Control Transfer Instruction.
                             // Required for MIPSR6
   bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
-  bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
-                            // ($pc) and with explicit offset and destination
-                            // register
   bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
                             // present in MIPS-I to MIPS-III.
 
@@ -107,8 +104,7 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
   let TSFlags{3-0}   = FormBits;
   let TSFlags{4}     = isCTI;
   let TSFlags{5}     = hasForbiddenSlot;
-  let TSFlags{6}     = IsPCRelativeLoad;
-  let TSFlags{7}     = hasFCCRegOperand;
+  let TSFlags{6}     = hasFCCRegOperand;
 
   let DecoderNamespace = "Mips";